Cache in CPUs

[imported_schwab]

So he's a kind of wacky question. In the Pentium 4, for example, there is 20k of on-die L1 cache and 1M of L2 cache on die. Since both of these caches are running at the same speed (say, 3.6Ghz), what's the point of keeping them separate? It made since when the caches were in different locations (say, L1 on die and L2 on the mobo) or ran at different speeds (L1 at full clock and L2 at 1/2 clock or whatever), but I'm wondering why it's still separate. Thanks for your help!

 

[InlineFive]

They are not the same. Both run at different speeds, L1 is the fastest and the L2 is slower, L3 is much slower, etc.

 

[imported_schwab]

Slower how? Time to search since each is getting bigger? That's the only thing i can think of since they both run at the same clock speed.

 

[mechBgon]

Welcome to the Forums schwab For a pretty in-depth look at caches, here's BurntKooshie's Fundamentals of Cache article.

 

[jagec]

Originally posted by: schwab
Slower how? Time to search since each is getting bigger? That's the only thing i can think of since they both run at the same clock speed.

because MHz isn't a good indicator of speed, there's also latency, data transfer rate, etc.

 

[Soulkeeper]

L1 cache takes more space on the silicon (atleast 5 times more space i believe)
on a P4 for example

the bandwidth of the L1 is well over 20GB/s and the L2 is in the teens ie: 16GB/s or 19GB/s ?
think it is 25% to 50% faster
anyways it's because the L1 has a wider path and can transfer "larger" amounts of data at the same clock
L1 is very expensive and this may be one of the reason why intel uses such a small L1 cache
also the L1 cache performs special tasks for other parts of the cpu pipeline (two different sections of L1 cache also)

the cache design is far more important than the size in realworld situations ie: games, rendering, etc

hope this helps

 

[imported_schwab]

Thank you all very much for your answers! I was pretty shocked to see that the P4 only has 20k of L1 cache and a whopping meg of L2 especially since the Celeron 370 has 32k of L1. I guess it all just depends how it's handled. Thanks again!

 

[gwag]

the L1 cache on a P4/P4 based celeron is not the same as any other CPU it has a trace cache measured in uOps.

 

[zephyrprime]

L1 cache takes more space on the silicon (atleast 5 times more space i believe)

I don't believe that's true. Also, the L1 often has more ports than the L2 so it can be access by more than one part of the CPU at a time.