C3 and C6 "report:" Seeking confident advice about effect on sleep states

[BonzaiDuck]

In some of the overclocking advice extant from the Sandy Bridge days, some sources actually advised turning off EIST and C1E as well as C3 and C6. But EIST and C1E had no real affect on OC'd stability.

Better advice noted that idle-level voltage stability benefited by turning off C3 and C6, and it was in fact advised to disable them especially when using Offset voltage settings.

What impact, if any, will disabling C3 and C6 have on (a) Sleep and (b) Hibernate, if "hybrid sleep" is disabled?

Does anyone have a "confident" answer for this?

 

[.vodka]

On the overclock part, I can tell you my experience. I OC my 2500k @ 4500MHz on offset voltage, and have C3 and C6 enabled. Mobo is an Asus Sabertooth P67. CPU power at idle drops to <5w, never had a single stability issue with these settings. At least with this particular motherboard, offset voltage and C3/C6 can coexist. Other P67/Z68 boards, I don't know, yet I did read about these two settings conflicting with any kind of OCing, even on stock!


I did find C3/C6 caused instability at idle for me trying to get higher than 4500MHz (>45x multiplier), so I decided to keep the CPU sipping power at idle with <1v, <5w, and get to 4500MHz, AVX stable, on 1.31v. I mean, I'd once tried 4800MHz on a little more voltage, it'd passed 5 hours of P95 AVX using 80-90% of free RAM. I'd stopped the test, left the computer alone for some coffee, came back and it'd crashed. Disabled C3/C6 and never had a single problem again at these speeds...

If I ever decide to get this to >4500MHz I'll have to get vcore up to a point to which I'm not very comfortable with, and get CPU idle power up to about 10w without C3/C6. Probably better cooling too (using a TRUE spirit 140 power right now, doesn't break a sweat at 4500MHz be it winter or summer)


You have a similar Asus board so I suppose C3/C6 behave in a similar way to what I've described when overclocking.

-------------

On the sleep and hibernate side of the coin, I don't use these, so I can't comment. Having a SSD has negated any need for me to sleep or hibernate, when the PC can do a cold boot in 15-20 seconds max.

 

[sm625]

If I ever decide to get this to >4500MHz I'll have to get vcore up to a point to which I'm not very comfortable with, and get CPU idle power up to about 10w without C3/C6.

So 5W with C3/C6 and 10W without C3/C6? Is that an estimate or did you take measurements for both conditions?

 

[Dufus]

I used to run my old 2500k with C3/C6 enabled, C1E disabled. With the cooling most I could run 4 cores heavily loaded was 4.6GHz but I also used stepped turbo's to give 5GHz when only one core was active. For stepped turbo bins across active cores at least C3 is needed. No instability although I used a fairly high voltage (extra turbo voltage) in conjunction with a lot of vdroop. Idle package power was about 5W IIRC. There may be problems with sleep and PLL overvoltage but I never needed that enabled for 5GHz.

 

[.vodka]

So 5W with C3/C6 and 10W without C3/C6? Is that an estimate or did you take measurements for both conditions?

Measurements taken from hwmonitor's data

Hm. <5w was from when I had the CPU at 4GHz on stock voltage, idle vcore then was at about 0.85-0.88v. Still, C3/C6 have a nice effect on idle power consumption / temperatures if you can enable them without bad side effects. Without them you jump at >10w idle CPU power.


Of course, Ivy, Haswell and soon Skylake have the idle power part improved a lot over good old Sandy.

 

[BonzaiDuck]

On the overclock part, I can tell you my experience. I OC my 2500k @ 4500MHz on offset voltage, and have C3 and C6 enabled. Mobo is an Asus Sabertooth P67. CPU power at idle drops to <5w, never had a single stability issue with these settings. At least with this particular motherboard, offset voltage and C3/C6 can coexist. Other P67/Z68 boards, I don't know, yet I did read about these two settings conflicting with any kind of OCing, even on stock!


I did find C3/C6 caused instability at idle for me trying to get higher than 4500MHz (>45x multiplier), so I decided to keep the CPU sipping power at idle with <1v, <5w, and get to 4500MHz, AVX stable, on 1.31v. I mean, I'd once tried 4800MHz on a little more voltage, it'd passed 5 hours of P95 AVX using 80-90% of free RAM. I'd stopped the test, left the computer alone for some coffee, came back and it'd crashed. Disabled C3/C6 and never had a single problem again at these speeds...

If I ever decide to get this to >4500MHz I'll have to get vcore up to a point to which I'm not very comfortable with, and get CPU idle power up to about 10w without C3/C6. Probably better cooling too (using a TRUE spirit 140 power right now, doesn't break a sweat at 4500MHz be it winter or summer)


You have a similar Asus board so I suppose C3/C6 behave in a similar way to what I've described when overclocking.

-------------

On the sleep and hibernate side of the coin, I don't use these, so I can't comment. Having a SSD has negated any need for me to sleep or hibernate, when the PC can do a cold boot in 15-20 seconds max.

I'd had idle instability so occasional on the sig-rig early last year that it was difficult to either replicate or troubleshoot. Perseverance somehow eliminated it, but I could never pinpoint the cause precisely.

The Twin 2700K here at my fingertips is showing similar problems since I added the second GTX 970 to it. I went back and reviewed the most authoritative guides posted on this very problem: Stop-code 124 on Sandy Bridge and Idle instability.

So far, I discovered that re-enabling Spread Spectrum makes the voltage more stable at idle, and less variable under load. Who would've thought?! First thing we habitually did from long ago was to disable it as soon as we got into the BIOS.

The sig-rig still has BIOS 606, which was the release prior to 707, and 707 fixed the problem with sleep-states and PLL-Overvoltage. The 2700 has the later Pro/Gen3 board and the very last BIOS published for it.

So this 2700K is getting some "shake-down cruises" and it's likely it will all be tip-top. I may back down the LLC about 20mV -- I'll see about that. But it means raising either Offset, Extra Voltage for Turbo, or both. And starting out, it will have be a "guesstimate" for compensating the extra droop.

Especially, this particular machine must be able to sleep for an hour, then hibernate. In hibernation, it must wake up properly when my WHS server wants to back it up in the wee hours. That's all working properly, but the occasional trouble seemed to arise at wake from hibernation. There were some USB peripherals that also needed some adjustment for this very situation. The UPS backup for each of these units have new batteries and are solid. And in fact, one of them was misconfigured: set to wake up my system. I don't need that, if they've hibernated.

I made a point to avoid enabling PLL_Overvoltage or upping the "Current Capability" on these systems. I was going to try for 4.8 with HT disabled on this puppy, but not so sure.

I suppose I've been spoiled, now that I've got all the machines in the house to sleep and wake properly excepting for the 24/7 sig-rig and WHS box.

 

[.vodka]

Try to back down to an easy 4.5GHz, then see how it behaves with C3/C6 + offset voltage. Flash the latest BIOS.

No need for PLL overvoltage unless you're shooting for >4800-5000MHz where some CPUs don't want to POST, even with enough vcore. BSOD 124 on Sandy is not enough vcore.

I remember this rig hanging when sleeping or hibernating (stock settings, or a simple 4GHz OC) during its first BIOS updates, then the problem went away with the later releases. Latest one for this particular board (sabertooth P67), 3602, is flawless. I haven't used sleep or hibernate for a while, yeah, but I remember it behaving much better after a certain BIOS update. It should be a similar situation for your two rigs.

If everything else fails, a stock 2500k/2600k isn't exactly slow, either. And most probably any remaining issue with sleep/hibernate should go away on a stock system + the latest BIOS.

 

[BonzaiDuck]

Try to back down to an easy 4.5GHz, then see how it behaves with C3/C6 + offset voltage. Flash the latest BIOS.

No need for PLL overvoltage unless you're shooting for >4800-5000MHz where some CPUs don't want to POST, even with enough vcore. BSOD 124 on Sandy is not enough vcore.

I remember this rig hanging when sleeping or hibernating (stock settings, or a simple 4GHz OC) during its first BIOS updates, then the problem went away with the later releases. Latest one for this particular board (sabertooth P67), 3602, is flawless. I haven't used sleep or hibernate for a while, yeah, but I remember it behaving much better after a certain BIOS update. It should be a similar situation for your two rigs.

If everything else fails, a stock 2500k/2600k isn't exactly slow, either. And most probably any remaining issue with sleep/hibernate should go away on a stock system + the latest BIOS.

Not being dismissive or "passive aggressive" about this. Dig deep enough, and there's even argument that the Stop-Code list isn't accurate. But 101 was always "definitely" VCORE. 9C often indicated either RAM or the IMC.

124 occurred for any variety of reasons. It could often be a false positive for hardware settings, because it's been known to occur with a buggy video driver, insufficiently-volted graphics card, other buggy or conflicting drivers. I think someone even concluded that the NVStreamService installed with your NVidia GPU software might trigger a BSOD with the same stop code.

Sometimes, a poor PLL Voltage setting or insufficient or TOO-HIGH VCCIO (IMC again) would cause it. I think there were a lot of 124 occurrences for "idle instability" because that's how those topics merge.

After those possibilities -- yes -- VCORE could cause it -- too much or too little. But idle instability is less likely to be a VCORE setting. More likely -- LLC, VCCIO and the c3/c6 settings.

What happens with these SB processors (not sure about IB, and Haswell would likely have made it less of a problem as someone already stated): too much LLC interacting with the Offset voltage setting would cause the transition between load and idle to swing far enough so that there is a momentary harmonic voltage dip (spike) causing voltage to drop below minimum needed to keep it stable.

And of course, one solution is to use less extreme LLC settings. On this board, they run from "Auto" or none, to "Regular" 25%, "Medium" 50%, "High," "Ultra" and Extreme. High seems to leave a residual vDroop of about 20 mV. So when fiddling with LLC, you'd see vDroop shrink by ~ 20mV for each higher setting.

Also, some people are too cavalier about setting the VCCIO, warned as they are not to go over 1.2V. But it's possible that the upper acceptable range -- say, 1.15V or higher -- can cause instability in conjunction with the PLL Voltage setting. And at some clock settings like mine, "Auto" @ ~1.00 or 1.05V won't cut it.

On the other hand, it's pretty much agreed by some that there's a sweet-spot below default PLL-voltage of ~1.8V, or somewhere between 1.67 and 1.70V. In fact, different motherboards and chipsets for the same processor may work better with PLL-V > 1.8. These boards seem to allow settings below the default.

 

[.vodka]

Well put, all of it. You know your Sandy rigs well.

Problem is, that's a lot of knobs to tweak until finding stability. I'd clear CMOS and give it a fresh start before going any further.

 

[BonzaiDuck]

I don't think so. If I did that, I'd compel myself to get the screen captures from the BIOS menus. When I switch to any of the five tested, validated setups, the still all behave the same.

But -- stuff to report.

I have hybrid sleep disabled. If C3/C6 affected any of the possible power-saving scenarios, that would be the one.

With C3/C6 disabled, I put it to sleep for maybe 10 minutes and it wakes up fine. Then I hibernated. Also fine. Proof of the pudding will be a return to its previous master-slave feature of the WHS networking, in the regular pre-set schedule.

Also, I changed Spread Spectrum to "Enabled."

The idle voltage now stays constant at a higher level -- therefore more stable.

I actually lowered VCCIO from a too-high setting, having crashed earlier with an attempt at "Auto" of 1.005 to 1.05V in the real-time monitor. It's now set at something near 1.1250V. It will mean more tweaks and tests if I want to change the RAM command rate to 1. It either needs more VCCIO or more VDIMM for that. Since the VDIMM is either "Auto" or something near 1.5V, a few more millivolts is not really outside the spec. It's just . . . trouble . . . But I know a good setting to try -- if I do.

Almost forgot to say. It ran 4.5 hours on OCCT:CPU, and I wasn't expecting that much stability. It had crashed in an hour for the previous setting. And all because of this diddly-shit I just explained.

 

[BonzaiDuck]

OK. OK.

As before, this seems rock-solid, but there are some indications that idle-instability with stop-code 124 may be gone. Since these instances were occurring maybe once a week, may have been associated with items waking up the machine which I definitely didn't want to behave that way, only time will tell. I figure two weeks of sleeping, hibernating and waking will prove it.

The fix is definitely a matter of disabling C3/C6, given the number of forum posts elsewhere, OC'ing guides and other sources. Since I re-enabled Spread Spectrum, that also could contribute to stability at both ends of speed and voltage swings.

Eliminate hybrid sleep, and the sleep and hibernate functions continue to work well.

Did any Sandy Bridge veteran manage to observe or record how much in extra Mhz you can buy with PLL_Overvoltage enabled, when no change is made in Offset or "Extra Voltage for Turbo?"

In other words, by enabling PLL_OVervoltage, could you "buy" an increase of +1 in the turbo multiplier without "paying" anything in voltage adjustment?

I'm going to try it anyway, but any info from someone else's experience would be helpful. I suppose if I did enable PLL_OV___, I'll need to give more attention to cooling the motherboard VRMs and related components.