Bulldozer: 213million transistors in 31mm^2?????

[deputc26]

At ieee ISSCC today AMD revealed that a one module (two "core") Bulldozer will have 213 million transistors and measure just 30.9 square mm including cache. This means AMD's 32nm transistors are packed much more tightly than on Intel's 32nm procs.

for reference, here's Intel's 32nm procs:
Gulftown: 1.17b transistors, 240mm^2 = 4.875million transistors/mm^2

Clarkdale: 384m transistors, 81mm^2 = 4.74million transistors/mm^2

Sandy Bridge 4C: 996m transistors, 216mm^2 = 4.611million transistors/mm^2

Sandy Bridge 2C: 504m transistors, 131mm^2 = 3.85million transistors/mm^2

and here's Bulldozer:

231m transistors, 31mm^2 = 7.45million transistors/mm^2

I know the node name (32nm) is really a marketing label but this means AMD is laying down transistors at about 166% the density of Intel. Could this be an AMD advantage at last? Or did they make sacrifices in other characteristics of the chip? In any case, at 31mm^2 these things should be CHEAP, that's like 6mm^2 bigger than Atom.

 

[itsmydamnation]

thats not a meaningful comparision, IO for example has a lot low density. unless intel publish transistors per core we can't make a comparision. that said a bulldozer core with around the same amount of cache as a SB core is around the same size.

 

[ShadowVVL]

I was hoping for 1bil transistors.
Im guessing bulldozer will be smaller or same size as phenom IIx4?

 

[dorion]

Is it still true that Intel can make denser cache than AMD like back in the Pentium 4/Core 2 days? That was the reasoning for Intel L2 cache superiority IIRC.

If that's still true I want to see these numbers vs. a Bulldozer core, ie. the L3 cache thrown in, or against a single Core... core(logic\L2 cache).

 

[gevorg]

I'm afraid comparing transistor counts/density is like comparing GHz between two different CPU architectures.

 

[Mopetar]

You really need to see the final product as the Bulldozer chips will have L3 cache and various other uncore parts added.

 

[Fox5]

Why are you comparing Bulldozer cores to Intel's entire processor package? Cores are very dense, and account for probably less than half the space on a die.

 

[deputc26]

You really need to see the final product as the Bulldozer chips will have L3 cache and various other uncore parts added.

This is what I was thinking, I understand this isn't an apples to apples comparison but given identical cache sizes with 2C SB, the general similarity of all Intel's 32nm parts and the relatively large gap of 66% I think there is some validity to the point.

 

[deputc26]

Why are you comparing Bulldozer cores to Intel's entire processor package? Cores are very dense, and account for probably less than half the space on a die.

The announcements made it sound like this is a complete 2C part (and cache is definitely included) perhaps I'm wrong but I see no reason to doubt it.

 

[acx]

Does Bulldozer module include transistors for integrated graphics?

 

[Arkadrel]

Does Bulldozer module include transistors for integrated graphics?

No, not the server ones or the ones for the desktop.
There probably will come APU's with bulldozer designs, but not the first ones out.

 

[tijag]

The announcements made it sound like this is a complete 2C part (and cache is definitely included) perhaps I'm wrong but I see no reason to doubt it.

You are wrong. The size given is just for 1 module, not for the rest of the chip. There will be a L3 cache and all other stuff not part of the given module size.

Unless you can compare the size of an intel 'core' to this BD core, the comparisons you're making are not valid.

 

[IntelUser2000]

The announcements made it sound like this is a complete 2C part (and cache is definitely included) perhaps I'm wrong but I see no reason to doubt it.

Microprocessor cores are too complex too judge its density on transistor count alone.

http://www.chip-architect.com/news/Llano_vs_SandyBridge_vs_Westmere.jpg

Westmere 1 core + 2MB L3: 28.5mm2

Let's assume it has half the transistors of dual core Clarkdale, or 384 million/2 = 192 million transistors

192 million transistors, 28.5mm2 = 6.74 million transistors/mm2

See how much difference it can make when just comparing the cores?

(BTW Atom is 10mm2 for core + 512KB L2)

 

[Soulkeeper]

"I know the node name (32nm) is really a marketing label"

Not a marketing label .... much more than that

 

[IntelUser2000]

"I know the node name (32nm) is really a marketing label"

Not a marketing label .... much more than that

There are parts of a transistor that comes close to, or even smaller than the node size indicates, like the thinner part of the device. However, there's no set relation of what that part is with the node name.

Nowadays, 32nm just means "2x the density of 45nm".

 

[Idontcare]

The announcements made it sound like this is a complete 2C part (and cache is definitely included) perhaps I'm wrong but I see no reason to doubt it.

Yeah you got to watch those sneaky announcements, seriously, they can easily overstate or mistate what was actually said and then it snowballs from there.

In this case what is being talking about is truly just the core itself plus the L1/L2$. None of the uncore stuff like the L3$ or memory controller, etc, are included.

The chip will be big, don't worry. An 8core zambezi might only require 124mm^2 for the cores but it will still end up being 260mm^2 after all the other stuff is added.

And yes, all else being equal (which they aren't), GloFo's gate-first HK/MG integration scheme is supposed to provide an estimated 10-20% higher gate density compared to a gate-last integration scheme. (this was stated in one of glofo's press slides at some point)

The argument was that they were trading off production cost for performance: higher xtor density (smaller die, less cost per die) but lower drive currents (larger die, better xtor performance).

We won't really know until bulldozer ships and the guys at Semiconductor Insights and Chipworks do their tear-down analyses.

 

[HW2050Plus]

Though the original post has the flaw of comparing core + L2 density with the density of a whole chip where the large power gating and IO areas consume much die size, it is obvious that there might be a density advantage.

We do not know how large the Bulldozer die gets, there are estimations out from 200 mm² to 360 mm².

I assume that it will end up at ~240 mm². But let us take more pesimistic values, 300 mm² for die are and 1.4 billion transistors.

With that we get a density of 4.67 million transistors per square mm.

That is roughly the same as Sandy Bridge. But that is a rather pesimistic estimation. If we take 240 mm² for die size and 1.35 billion transistors we will end up with 5.6 million transistors per mm².

So maybe they are more dense, maybe not, we will have to wait.

On the other hand what does this more dense means?
Basically nothing!
First as cache is always more dense than logic and as rumors suggest AMD found some very efficient SRAM cell for caches it could just be the reason that you have more cache per chip area on BD than on SB (6 MB more).

The important thing will be the die size. And there I do not see any advantage for AMD.

Anyway the AMD 32 nm process is superior because of SOI and the Intel advantage of high k metal gate has been now incorporated by AMD since Intel still used bulk instead of SOI. So Intel has a time advantage for it's process and AMD has some advantage from SOI.

 

[deputc26]

Westmere 1 core + 2MB L3: 28.5mm2

Let's assume it has half the transistors of dual core Clarkdale, or 384 million/2 = 192 million transistors

192 million transistors, 28.5mm2 = 6.74 million transistors/mm2

See how much difference it can make when just comparing the cores?

(BTW Atom is 10mm2 for core + 512KB L2)

Yeah you got to watch those sneaky announcements, seriously, they can easily overstate or mistate what was actually said and then it snowballs from there.

In this case what is being talking about is truly just the core itself plus the L1/L2$. None of the uncore stuff like the L3$ or memory controller, etc, are included.

The chip will be big, don't worry. An 8core zambezi might only require 124mm^2 for the cores but it will still end up being 260mm^2 after all the other stuff is added.

And yes, all else being equal (which they aren't), GloFo's gate-first HK/MG integration scheme is supposed to provide an estimated 10-20% higher gate density compared to a gate-last integration scheme. (this was stated in one of glofo's press slides at some point)

The argument was that they were trading off production cost for performance: higher xtor density (smaller die, less cost per die) but lower drive currents (larger die, better xtor performance).

We won't really know until bulldozer ships and the guys at Semiconductor Insights and Chipworks do their tear-down analyses.

Thanks IDC and IntelUser, I think that about clears it up!