Broadwell to Skylake, will be similar to the transition from Prescott to Conroe

[mizzou]

I was talking with somebody who is still using an X2 4200+ in 2015 recently. I nearly collapsed. :awe:

Until benches are out speculation is just that. Skylake could be 5% faster or 55% faster. Only Intel knows.

My 2nd computer is still running a X2

 

[Idontcare]

I would bet it will be more like 5% again. In fact I bet Intel has all of the gains for the next 3 or 4 processors laid out in a very methodical manner. Since there isn't any competition there isn't any reason to "let it all go" at once.

Intel Lowers Its Q1'15 Outlook On Account Of Weakening PC Demand

http://www.forbes.com/sites/greatspeculations/2015/03/13/intel-lowers-its-q115-outlook-on-account-of-weakening-pc-demand/

Intel's competition are the very CPUs it sold over past years. The world is full of 32nm Sandy Bridge customers who aren't quite convinced to upgrade to a Haswell refresh SKU.

If they approach the market as you are suggesting then they can expect lower and lower revenue as the shippable units drops from the resultant lack of demand.

I don't think Intel intentionally rolls out innovation in incremental fashion for the sake of stagnating today's sales on the premise that it will make tomorrow's sales a little bit higher than they would have otherwise been.

They want all that revenue now.

But I am sure they manage projects from a risk/reward perspective and it is very risky to throw a whole slew of unproven features into a spanking new "let it all go" product. Tick-tock itself is a risk-management approach, its very existence is proof positive that Intel is approaching changes in a very risk-conservative fashion.

Tick-tock isn't done so they can roll out 5% improvements and have the customers upgrade for lack of competition. They are acutely aware that 5% improvements makes for a lack of demand scenario as all the headlines reflected when Intel was forced to announce their guidance adjustment.

 

[frozentundra123456]

good post. In addition to themselves intel is also desperately competing with ARM in the phone and tablet space. Can anyone really reasonably believe that intel has some huge performance increase they are holding back in this sector?

 

[mikk]

Broadwell desktop is codenamed BDW-S. That is cancelled, as I've shown you.

BDW-S was never announced, how can this be cancelled? Even in old Roadmaps there wasn't such a thing, only BDW-K.

 

[erunion]

BDW-S was never announced, how can this be cancelled? Even in old Roadmaps there wasn't such a thing, only BDW-K.

Or it was simply cancelled early enough that it never appeared on public roadmaps.

Haswell Refresh appeared on roadmaps at least as early as June 2013! Before Broadwell -K did.

Its improbable that Intel being stuck on Haswell for 2 years was a deliberate plan.

 

[jhu]

Historically, that was one of the biggest jumps in performance Intel has ever seen, though really the fair comparison was Presler to Conroe (Presler was the prevailing Intel desktop dual-core at the beginning of 2006, even if not very many people bought them). And of course you can see them in the above-posted chart as the PentiumD 950 and 960.

Just looking at the 960 vs the E6700 (3.6 ghz vs 2.66 ghz), the increase in IPC is massive just in Quake4 alone. I would be shocked if Skylake could show up at, oh I don't know 3 ghz and put up gains of nearly +55% vs a hypothetical 4 ghz Broadwell in a video game. At that point, the so-called "14 nm clockspeed problem" that Intel is allegedly having wouldn't matter a whit.

Here are bigger ones:
86 -> 286
286 -> 386
386 -> 486
486 -> Pentium

 

[jhu]

Intel's competition are the very CPUs it sold over past years. The world is full of 32nm Sandy Bridge customers who aren't quite convinced to upgrade to a Haswell refresh SKU.

If they approach the market as you are suggesting then they can expect lower and lower revenue as the shippable units drops from the resultant lack of demand.

I don't think Intel intentionally rolls out innovation in incremental fashion for the sake of stagnating today's sales on the premise that it will make tomorrow's sales a little bit higher than they would have otherwise been.

They want all that revenue now.

But I am sure they manage projects from a risk/reward perspective and it is very risky to throw a whole slew of unproven features into a spanking new "let it all go" product. Tick-tock itself is a risk-management approach, its very existence is proof positive that Intel is approaching changes in a very risk-conservative fashion.

Tick-tock isn't done so they can roll out 5% improvements and have the customers upgrade for lack of competition. They are acutely aware that 5% improvements makes for a lack of demand scenario as all the headlines reflected when Intel was forced to announce their guidance adjustment.

I'm not sure why people don't understand this. Do people really like adhering to the Intel conspiracy theory so much?

 

[mizzou]

Here are bigger ones:
86 -> 286
286 -> 386
386 -> 486
486 -> Pentium

I remember the difference being so ungodly different. What an amazing time to be a PC it was!

https://www.youtube.com/watch?v=tlj8Qyl1Sf0

 

[MountainKing]

486 to pentium was massive....
So was Pentium D to conroe?

 

[VirtualLarry]

I would bet it will be more like 5% again. In fact I bet Intel has all of the gains for the next 3 or 4 processors laid out in a very methodical manner. Since there isn't any competition there isn't any reason to "let it all go" at once.

What they seem to be doing it over engineering one or two parts of the CPU to increase IPC so that the bottleneck is not only gone but opens things up so much that another area becomes the bottleneck, which is then opened up on the next iteration.

Intel could have done this all at once but there was no need.

For example, new branch predictor for Sandy Bridge.
Then Ivy gets dynamically partitioned internal structures and prefetcher improvement.
Then Haswell gets a wider execution engine...

And then what? If AMD becomes totally uncompetitive in desktop and mobile x86/x64 (they are dangerously close to that now), will Intel stop giving us 5% gains, and move to only introducing new ISAs / opcodes (doling them out, one new one per arch), giving us potential gains, only if we both buy their top-end CPUs, and buy new software.

My take on the opcode situation, is that Intel could have allowed their CPU generations to have ALL the new opcodes, from the top to the bottom of their product stack, per that generation, and actually encouraged usage of the new opcodes, thus producing market demand for their new generations of CPUs.

What we have now, is most software rarely, if ever, uses anything newer than SSE2 (introduced in what, PIII or P4?), and ARM is growing by leaps and bounds, nipping at Intel's market heels, and even making inroads to servers.

If server software used the new opcodes heavily, this would be far less likely to happen.

 

[jhu]

486 to pentium was massive....
So was Pentium D to conroe?

Those of us who went from Yonah to Conroe didn't see such significant gains other than 64-bit.

 

[Idontcare]

486 to pentium was massive....
So was Pentium D to conroe?

For me, 486 to Pentium was not as massive an upgrade as was my 486 25MHz to 486 100MHz upgrade.

But I agree that in general, anyone upgrading to pentium-class compute from 286/386/486 platforms experienced quite the wild ride.

That decade was golden. Now we get maybe 5-10% IPC improvement per annum, and lately we get (as OC'ing enthusiasts) retrograde or degrading clockspeeds.

I'm hoping that someday in the next 5 years Intel decides to direct its engineers to either develop a process node that increase fmax or to design a circuit that can compute "A+B=" 2x faster than today's processor can. (is 2x improvement over 5 years too much to expect anymore? I kinda feel like it is )

 

[AtenRa]

Intel's competition are the very CPUs it sold over past years. The world is full of 32nm Sandy Bridge customers who aren't quite convinced to upgrade to a Haswell refresh SKU.

The one customer that continuously upgrades his PC hardware are the enthusiasts Gamers.
Now, as thinks are progressing in the PC Gaming world (DX-12, 4K resolutions, 6-8 threaded Gaming Engines etc) the CPU upgrades become less and less important for gamers with Sandy/Ivy CPUs.
GPUs are becoming more and more the dominant hardware to be upgraded in the lifespan of a Gamers PC system not the CPU.
Every game is playable with a SandyBridge Core i3 paired with a high-end dGPU like Maxwell and Hawaii TODAY and will be in the coming years. Im sure that most people here with OCed Sandy/Ivys would upgrade their GPUs TODAY and dont think upgrading the CPU for at least a couple of years.

Higher than 1080p Monitors are becoming cheaper and cheaper and 4K Monitors will become the new standard format in a few years. Combine that with DX-12, and a 4-4,5GHz SandyBridge will be enough for 1440/4K gaming for the next 2-3 years if you have the appropriate GPU.

The problem Intel is facing currently here is not from the Gaming/enthusiasts Desktop market but from the Mobile/Laptop and the Corporate Segments.
The vast majority of Customers in those segments are fine with a 2GHz dual core CPU, those people dont even have a problem operating devices with 1.3-1.6GHz ARM CPUs.
Why do they need to upgrade in a era of world austerity when they can use what they already have to do their jobs ??

All the above are the reasons Intel is trying to get a foot in the Mobile market. Desktop volume is shrinking, only the gaming segment is doing ok and not in CPUs. The future is Mobile and the reason Intel introduced 14nm Core M first.

 

[DownTheSky]

Found this review. Doesn't have the 486 but it's pretty f cool.
http://www.tomshardware.co.uk/benchmark-marathon,review-640.html

 

[Nothingness]

Skylake does however have a noticeable boost in multithreaded performance. I am currently attributing this to a couple of changes that are likely to make in into Skylake (pulling from RWT's David Kanter here), the first being a shift to a "tiled" cache hierarchy, where L2 is shared between cores in groups of two, much like Bulldozer (arguably), and Apple's Cyclone. Sharing L2 between two cores is something that Intel has not chosen to do since they bolted an L3 cache on. It's not uncommon to see the L2 shared in L3-less chips (in fact, it's really all you'll ever see), however Intel chose a different route on chips with L3 included. They might be going back to a shared L2, and I think that's a smart move.

The other change that Kanter alluded to was a change in the interconnect fabric: from the current ring bus, to a 2D mesh. I don't really know many of the details surrounding this, although I'm fairly certain it'd be a good improvement to inter-core communication, as I recall ring buses being a pretty outdated concept.

Did you carefully study Geekbench behavior in multithread? Are you sure it shares (modified) data across threads? If not, sharing L2 and/or having different interconnect topologies should have a very small impact on Geekbench MT score.

 

[jpiniero]

And then what? If AMD becomes totally uncompetitive in desktop and mobile x86/x64 (they are dangerously close to that now), will Intel stop giving us 5% gains, and move to only introducing new ISAs / opcodes (doling them out, one new one per arch), giving us potential gains, only if we both buy their top-end CPUs, and buy new software.

I imagine you will see more gimmicks like the wireless charging in Skylake.

 

[podspi]

I imagine you will see more gimmicks like the wireless charging in Skylake.

When efficiency isn't a priority, wireless charging is actually pretty awesome.

Especially if you could get it integrated into tables, etc, I can see that as being an awesome feature in libraries, coffee shops (read:starbucks), etc.

 

[mikk]

Or it was simply cancelled early enough that it never appeared on public roadmaps.

Haswell Refresh appeared on roadmaps at least as early as June 2013! Before Broadwell -K did.

Its improbable that Intel being stuck on Haswell for 2 years was a deliberate plan.

Don't post speculation as a fact. You can't prove that Intel cancelled BDW-S.

 

[podspi]

Intel's competition are the very CPUs it sold over past years. The world is full of 32nm Sandy Bridge customers who aren't quite convinced to upgrade to a Haswell refresh SKU.

If they approach the market as you are suggesting then they can expect lower and lower revenue as the shippable units drops from the resultant lack of demand.

I don't think Intel intentionally rolls out innovation in incremental fashion for the sake of stagnating today's sales on the premise that it will make tomorrow's sales a little bit higher than they would have otherwise been.

They want all that revenue now.

But I am sure they manage projects from a risk/reward perspective and it is very risky to throw a whole slew of unproven features into a spanking new "let it all go" product. Tick-tock itself is a risk-management approach, its very existence is proof positive that Intel is approaching changes in a very risk-conservative fashion.

Tick-tock isn't done so they can roll out 5% improvements and have the customers upgrade for lack of competition. They are acutely aware that 5% improvements makes for a lack of demand scenario as all the headlines reflected when Intel was forced to announce their guidance adjustment.

This point is made on this forum a lot, and while it isn't wrong, it also oversimplifies things to the point where it could be considered wrong. CPUs are not perfectly durable, and as a result while Intel does face intertemporal competition from itself, this will not result in the same outcome as competition from another, actual company. This is in terms of price, as well as rate of innovation.

Another point that has been made on this forum often is that there is are tradeoffs between R&D expenses, project schedule, project risk, and quality. While the stock of already sold CPUs prevents Intel from acting like a one-shot monopolist, competition from AMD and ARM certainly move Intel in the 'right direction' wrt these tradeoffs (from the consumers perspective).

 

[DrMrLordX]

Here are bigger ones:
86 -> 286
286 -> 386
386 -> 486
486 -> Pentium

Dunno if I'd say "bigger", though the clockspeed increases alone made up a lot of the advancement up 'til the Pentium launch. The Pentium was a pretty big deal since the original 60mhz monster was running at less than half the clockspeed of a 486dx133 and still kicking its butt (well, in fp workloads anyway).

Yeah Intel gained a lot of ground back then. Everything past the p54c/p55c got more . . . complicated.

The thing so extraordinary about moving from Presler to Conroe (Yonah was a pretty niche chip, though it was nice) was the dip in clockspeed didn't stop the next gen from stomping the previous gen flat. Kind of like what happened with the Pentium actually.

 

[crashtech]

It would be nice if we were on the cusp of something bigger, a real paradigm shift. What we have going on at the moment seems to be just sputtering along. Then again, this pause might be the only thing between us and the Singularity.

 

[ninaholic37]

I don't think Intel intentionally rolls out innovation in incremental fashion for the sake of stagnating today's sales on the premise that it will make tomorrow's sales a little bit higher than they would have otherwise been.

They want all that revenue now.

Hmmm... I could have sworn that you once said (a few years ago) that Intel already had all the innovations planned out to 7nm and beyond, and were just playing the economics/financials game (this might have been were Hulk got the idea for his post, ironically). Or maybe I'm misremembering things. Broadwell and Cherry Trail certainly seemed to have exposed the true reality that it's not all sunshine and rainbows in their 5-10 year plan though, unless these delays and misfortunes were all part of their long term $$$ strategy. :sneaky:

 

[Exophase]

I'm hoping that someday in the next 5 years Intel decides to direct its engineers to either develop a process node that increase fmax or to design a circuit that can compute "A+B=" 2x faster than today's processor can. (is 2x improvement over 5 years too much to expect anymore? I kinda feel like it is )

Prescott could literally compute A+B about twice as fast (half the effective latency) as Haswell today and with the same throughput. Fat lot of good that did it.

 

[Hulk]

Intel's competition are the very CPUs it sold over past years. The world is full of 32nm Sandy Bridge customers who aren't quite convinced to upgrade to a Haswell refresh SKU.

If they approach the market as you are suggesting then they can expect lower and lower revenue as the shippable units drops from the resultant lack of demand.

I don't think Intel intentionally rolls out innovation in incremental fashion for the sake of stagnating today's sales on the premise that it will make tomorrow's sales a little bit higher than they would have otherwise been.

They want all that revenue now.

But I am sure they manage projects from a risk/reward perspective and it is very risky to throw a whole slew of unproven features into a spanking new "let it all go" product. Tick-tock itself is a risk-management approach, its very existence is proof positive that Intel is approaching changes in a very risk-conservative fashion.

Tick-tock isn't done so they can roll out 5% improvements and have the customers upgrade for lack of competition. They are acutely aware that 5% improvements makes for a lack of demand scenario as all the headlines reflected when Intel was forced to announce their guidance adjustment.

Yes you are absolutely correct it IS all based on risk/reward. My point is that the lack of competition allows them to methodically lay out improvements over a few generations to reduce risk.

If AMD had a better performing part right now they would increase their risk and lay everything they had into a new part.

Like they did with Conroe.

It wouldn't be good business practice to start "jumping fences" to get a bigger lead when you're already winning the race because you could trip and fall. Again risk vs. reward.

 

[JoeRambo]

Prescott could literally compute A+B about twice as fast (half the effective latency) as Haswell today and with the same throughput. Fat lot of good that did it.

I am pretty much certain that Prescott removed dual pumped ALUs. And anyway all stars had to be aligned perfectly for P4 to make use its dual pumped ALUs properly. It was glass jawed paper tiger.