Broadwell architecture seems fundamentally clock limited

[mikk]

Ivy Bridge was the first architecture with a fully integrated voltage regulator (FIVR)

Haswell was the first.

 

[BigDaveX]

Ivy Bridge was the first architecture with a fully integrated voltage regulator (FIVR)

Sandy Bridge -> Ivy Bridge = Huge reduction in average attainable overclock (over 500mhz), oddly enough coinciding with the introduction of FIVR!

Sorry, but that's incorrect. The thing that Ivy Bridge introduced (aside from an iGPU that was able to make games not look like complete crap) was 3D tri-gate transistors, and it overclocked worse than Sandy Bridge because Intel started using thermal paste to attach the IHS instead of solder. Ivy Bridge-E, which did use solder, overclocked to pretty much the same speeds as Sandy Bridge-E.

 

[cytg111]

Is this still the case or have the situation improved?

 

[frozentundra123456]

Sorry, but that's incorrect. The thing that Ivy Bridge introduced (aside from an iGPU that was able to make games not look like complete crap) was 3D tri-gate transistors, and it overclocked worse than Sandy Bridge because Intel started using thermal paste to attach the IHS instead of solder. Ivy Bridge-E, which did use solder, overclocked to pretty much the same speeds as Sandy Bridge-E.

It was a new, mobile oriented process node as well, designed for power savings instead of absolute performance. Not sure you can attribute the entire loss of overclocking headroom solely to the TIM.

I dont recall much difference between HW and HW-E in overclocking, maybe a couple hundred mghz at most, and the same is true for BW-E.

 

[Nhirlathothep]

you need more info before think about bw limits

 

[Byte]

Skylake-E it is then!

 

[VirtualLarry]

Broadwell (and probably the process as well) was likely tuned for reduced power use at the expense of maximum clocks.

Hence, Xeon-D family.