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Big News for Intel Huh ?

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The big focus of the article is showing how Intel can make future GP Processors that can take in x86 instructions and convert them to other ISA formats.

Translation at runtime ruins performance of what the Intel presenter described as non-regular algorithms working on scalable datasets. The increase in time is too much.

Finance and Business Applications, as the presenter described, can handle translation, because the performance of the application is on an order big enough due to many factors such as simultaneous users, application depth, and highly varying data sets that using Java J2EE and translating bytecode at runtime will not significantly increase the time percentage-wise.

But geometry calculations encoded into x86 then translated into a vector-based ISA in the pipeline doesn't make a whole lot of sense.
 
Plus the blog article, due to its date, suggests the innovation describes inspired future chips. Not the Core Duo and Core 2 Duo. Sure they take advantage of a 64-bit bus but that hardly is a step in ISA translation not to mention VLIW ISA's.

 
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How Fast Will It Be?
Like the Transmeta devices, software will not run at it?s full potential until it?s been fully translated, you can pretty much bet Intel will make sure third party bench-markers will be made well aware of this. I suspect we may also see speculative translation running in the background so everything gets translated and saved as soon as possible. Once translated, the new binaries are saved to disc, they will run as native VLIW thereafter.

The forte of this processor will be multithreaded code and multitasking. If you are doing lots of things at one you?ll be well happy, servers in particular will benefit from this approach. Multitasking will benefit because different cores will get different tasks, a user switching between them will not cause them to halt so responsiveness of systems with this processor will be very good.

Single threaded performance on the other hand could be relatively weak although that?s not a given,

Intel has the ability to add Vector unit to a multucore processor. Such as maybe Nehalem . We get more info next week. Co processors and the such. With lots and lots of shared cache.

Now take a look at recent articles on intel and Ray tracing . Its like a jigsaw puzzle we just need to fit the piecies together.
With mitosis single threaded performance will be greatly enhanced. Ya I know it a leap . But the pieces are there its just puttung them together and seeing what the puzzle is all about. Intel has said that HT on nehalem won't be anything like we have seen before. So mitosis is a possiability.

Speculation is cool . Its really cool when there is info out their that can support ideas. Next week after IDF its going to be much more clear.
 
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