Before you go and buy a conroe.. think about this

[harpoon84]

I think both AMD and Intel got caught up in the '10GHz' buzz, it seems around 03 both claimed they would reach 10GHz and both are nowhere NEAR it, in fact we're not even 1/3 the way there yet (fastest C2D is 2.93GHz, fastest FX is 2.8GHz).

If we reach 10GHz by 2010 I'd be very surprised, considering how much clockspeed advances have stagnated in recent years. A64: 2GHz in 03, 2.8GHz in 06... wow! Not...
P4 is even worse... 3.2GHz in 03, 3.8GHz in 06... FFS 600MHz in 3 years, nice work?!

10GHz my monkey ass...

 

[dexvx]

Originally posted by: Viditor

Originally posted by: ViditorI don't know why you think that the C2D's shared cache has an advantage over the Directly Connected cache of AMD, but it doesn't. There is an advantage to the SIZE of Intel's cache, but it isn't that much in most cases (say 5%).

The Core 2 Duo's two cores use one single pool of L2 cache. Worst case scenario, if you buy an Allendale with half of the L2 cache, either of the cores can still use the entire 2mb L2 cache with the other core helping or sitting idle. It is an inherent physical advantage. I expect the private L2 cache approach by AMD will work, but it won't work as efficiently as Intel's fully shared cache. Then again AMD's chips don't really need cache, so the 2mb L3 pool of cache might work great, I can't really say.

There really is no advantage to a shared cache over 2 directly connected caches. Unlike the seperate caches found on the 8xx and 9xx Pentium Ds, AMD has a crossbar within the processor for direct cache coherency (the PDs need to go through the FSB and back).

Shared L2 does have a very good advantage over the cross-bar design (and hence why AMD is moving towards shared cache in K8L). The L2 hits will have a delay in the 10s of NS. The cross-bar operates at the frequency of the processor. So even at 3Ghz, it'll still have a hit of around 200 NS.

Originally posted by: Viditor
There are many more differences between Opteron and X2 than most in the consumer market would understand (even enthusiasts). Most of this has to do with what is called RAS (reliability, availability, and serviceability), and it's VERRRRRY important to mission critical servers (but not at all to consumer systems). Basically it is various "hooks" that allow a system administrator to monitor and adjust the system remotely at highly granular levels.
This is why a Xeon 5130 (2GHz Woodcrest) sells for $350, and the e6400 (2.13GHz C2D) sells for $264...only the Opteron has many more RAS features than the Woodcrest, so the difference is even greater (Intel assigns many of their RAS features to the chipset rather than the CPU).

I would argue they are the same. The only difference is that they have different Q&A standards. FYI, the Woodcrest 3Ghz is MSRP $969 and the X6800 2.93Ghz MSRP is $1049.

 

[imported_Questar]

Originally posted by: Furen

Originally posted by: Questar
Fred Weber's presentation at the 2003 Microprocssor forum. Here's his feature list:
Threaded architectures;
Chip level multiprocessing;
Huge scale MP machines;
10GHz operation;
Much higher performance superscalar, out of order CPU core;
Huge caches;
Media/vector processing extensions;
Branch and memory hints;
GHz performance IO;
Security and virtualization;
Static and dynamic power management

http://www.xbitlabs.com/news/cpu/display/20031016140742.html

He also said that this would be part of FUTURE microarchitectures, as in K9+. There was no timeline given for these improvements, nothing like "We'll have 10GHz by 2004". Also, many of these improvements have already been implemented or will be implemented soon enough.

That exactly my point. K9 was cancelled shortly after his speech. K10 was cancelled in 2005.

How far in the future do you think he meant, 40 years?

 

[Kougar]

Just incase anyone hasn't seen it, http://en.wikipedia.org/wiki/AMD_K10 was interesting to scan through. While the quote given at the top can be taken to reference K10, I'm far more inclined to believe he is directly referring to K8L, since it is being released in 2007. Even so it is a sure thing AMD has design plans they have been working on for the chip that will replace K8L, and that one is supposedly "K10". The wiki on "K9" seems to be sure the chip design was cancled and rolled into K10.

Originally posted by: Viditor
Your point on increasing the FSB speed makes sense at first blush, but you are forgetting that you are also adding more cores and data. This means that the FSB has to do much more work with a quad core than it does on a dual core. In addition (as Furen pointed out), the Kentsfield is 2 Conroes glued together...this means that cache coherency between the 2 shared caches must go through the FSB as well. While I have no doubt that this will be no problem, it will most likely limit the amount you will be able to increase the FSB (and all things being equal, be a bit slower than a native quad core).

I am not forgetting that, and I understand that a faster clocked quad core inherently means a heavier FSB traffic load. But I believe that rasing the FSB itself will STILL yield more bandwidth for use The coherency traffic between the CPU and the northbridge is a major part of the bandwidth limitation problem, not a separate problem.

As far as increasing the FSB, I think the FSB is much less "unstable" than Intel gives the impression of it being. The primary problem with high FSB overclocks is that the Northbridge is simply not designed with the correct internal clock strap ratios to set itself at a low enough mhz. The northbridge is basically a CPU in-miniture with it's own core mhz that raising the FSB will upset.

Some motherboard manufacturers have invested in adding the extra modifications to the chipset itself to enable more direct control of this internal MCH clock/FSB strap or ratio, and will lower it to match the higher FSB speeds.

I am currently able to run a E6300 at 3.5ghz on air. That gives me a 501FSB, 2,000mhz QDR. CPU voltage was only 1.36v, and the only reason I did not go higher because I need watercooling! This motherboard has this built in option to "underclock" the MCH, then the "underclocked" MCH is overclocked with the higher FSB speeds.

Gigabyte includes a "FSB Overvoltage" setting and also a "MCH Overvoltage" setting on the GA-965P-DS3. To attain a 501FSB overclock I did NOT have to raise the FSB or MCH voltage from stock! This tells me that if you redesign the chipset with extreme FSB's in mind, then it is possible. I can actually run a 486FSB stable 24/7 for folding, but at 3.5ghz my E6300 needs more vCore, which I won't give due to the 51-58c temps I am getting at 1.36v.

 

[Furen]

Originally posted by: dexvx
Shared L2 does have a very good advantage over the cross-bar design (and hence why AMD is moving towards shared cache in K8L). The L2 hits will have a delay in the 10s of NS. The cross-bar operates at the frequency of the processor. So even at 3Ghz, it'll still have a hit of around 200 NS.

200ns? Nice made up number. An Opteron can hit ANOTHER OPTERON's memory in much less than that. 200ns on a 3GHz Opteron is something like a 600 cycle delay. AMD is moving to shared L3, to, basically will just lessen crossbard and memory controller utilization. It also allows AMD to increase cache "significantly" with lower density SRAM and without having to increase the cache of each of the 4 core.

 

[Viditor]

Originally posted by: Questar

Originally posted by: Viditor

Originally posted by: Questar


AMD also said they would be at 10Ghz, have SMT, and huge caches. Where did all that go? Must have been in the cancelled K9 and K10.

Link?
BTW
1. K10 isn't cancelled
2. SMT is a subset of SMP (multicore)
3. Huge caches (L3) are being released in mid 2007
4. AMD has never said anything about 10GHz (in fact, that's a fairly silly comment...)

Link?
Fred Weber's presentation at the 2003 Microprocssor forum. Here's his feature list:
Threaded architectures;
Chip level multiprocessing;
Huge scale MP machines;
10GHz operation;
Much higher performance superscalar, out of order CPU core;
Huge caches;
Media/vector processing extensions;
Branch and memory hints;
GHz performance IO;
Security and virtualization;
Static and dynamic power management

http://www.xbitlabs.com/news/cpu/display/20031016140742.html

1. Then were is it? Assuming development started when K9 was cancelled it would be a 2007 chip. There is no mention of it in AMD roadmaps through 2008.

2. No, it's not.

3. A few megs are huge?

4. Actually it's silly of you not to Google before you reply and are proven wrong. Google just a little bit more and you can actually find the slides from his preseataion saying AMD would be at 10ghz by now.

1. I have no idea where you are inventing these numbers from...if you take the date when you are assuming K9 was cancelled (I believe it was morphed into K8L, but whatever...), then add 5 years (the amount of time it takes to develop a chip design for market), then I guess you think the K9 was "cancelled" in 2002?

2. A nice, short, unsubstantiated, and incorrect answer...

3. Hmmm...200%-400% larger than current L2 seems fairly big to me. Of course it is an expandable L3 as well, so 8MB+ isn't beyond the realm of possibilities.

4. Please link where he said they would be at 10GHz now...

 

[RichUK]

AMD might still surprise us with the implementation of Z-ram on their future processors. They have already licensed this tech for research about a year ago.

This would result in some very very dense level 3 Cache if ever to be implemented. In fact I believe it has a ratio of 6:1 (S-ram: Z-ram) on a transistor count basis within each cell. Although Z-ram requires less transistors per cell (I think it only requires 1) it will be slower than current S-ram technologies. So depending on implementation it could be on par with L2 cache performance or a tad bit under par, either way it will provide a hell of a lot more bandwidth and reduced latency compared to D-ram.

Just think on 65nm, AMD could even implement 8MB+ of L3 cache. This could considerably cut down main memory access/requests, and in scenarios such as top level game playing, perhaps such games as UT2007 etc, it could speed up performance considerably.

 

[dmens]

Originally posted by: Viditor

Originally posted by: Questar

Originally posted by: Viditor
2. SMT is a subset of SMP (multicore)

2. No, it's not.

2. A nice, short, unsubstantiated, and incorrect answer...

How can you call SMT a "subset" of SMP when, core resources are shared or partitioned, including L* caches, which is contradictory with the definition of symmetric multiprocessing? SMT is opportunistic, SMP is designed to be balanced.

 

[imported_Questar]

Originally posted by: Viditor

Originally posted by: Questar

Originally posted by: Viditor

Originally posted by: Questar


AMD also said they would be at 10Ghz, have SMT, and huge caches. Where did all that go? Must have been in the cancelled K9 and K10.

Link?
BTW
1. K10 isn't cancelled
2. SMT is a subset of SMP (multicore)
3. Huge caches (L3) are being released in mid 2007
4. AMD has never said anything about 10GHz (in fact, that's a fairly silly comment...)

Link?
Fred Weber's presentation at the 2003 Microprocssor forum. Here's his feature list:
Threaded architectures;
Chip level multiprocessing;
Huge scale MP machines;
10GHz operation;
Much higher performance superscalar, out of order CPU core;
Huge caches;
Media/vector processing extensions;
Branch and memory hints;
GHz performance IO;
Security and virtualization;
Static and dynamic power management

http://www.xbitlabs.com/news/cpu/display/20031016140742.html

1. Then were is it? Assuming development started when K9 was cancelled it would be a 2007 chip. There is no mention of it in AMD roadmaps through 2008.

2. No, it's not.

3. A few megs are huge?

4. Actually it's silly of you not to Google before you reply and are proven wrong. Google just a little bit more and you can actually find the slides from his preseataion saying AMD would be at 10ghz by now.

1. I have no idea where you are inventing these numbers from...if you take the date when you are assuming K9 was cancelled (I believe it was morphed into K8L, but whatever...), then add 5 years (the amount of time it takes to develop a chip design for market), then I guess you think the K9 was "cancelled" in 2002?

2. A nice, short, unsubstantiated, and incorrect answer...

3. Hmmm...200%-400% larger than current L2 seems fairly big to me. Of course it is an expandable L3 as well, so 8MB+ isn't beyond the realm of possibilities.

4. Please link where he said they would be at 10GHz now...

Are you saying it takes AMD 5 years to develop a CPU? If that's the case, then my argument still stands, as you know as well as I do that K9 was cancelled in 2003. There is not a new architecture on the AMD road maps through 2008. Also, it puts AMD in a world of hurt since Intel is on a four year schedule.

 

[Viditor]

Originally posted by: dmens

How can you call SMT a "subset" of SMP when, core resources are shared or partitioned, including L* caches, which is contradictory with the definition of symmetric multiprocessing? SMT is opportunistic, SMP is designed to be balanced.

By looking at it functionally...SMP allows for the simultaneous processing of multiple threads at all times, whereas (as you say) SMT does the same thing when the opportunity presents itself.

 

[Viditor]

Originally posted by: Questar

Are you saying it takes AMD 5 years to develop a CPU? If that's the case, then my argument still stands, as you know as well as I do that K9 was cancelled in 2003. There is not a new architecture on the AMD road maps through 2008. Also, it puts AMD in a world of hurt since Intel is on a four year schedule.

It takes both Intel and AMD approximately 5 years to develop a CPU. As to K9, I never have seen a cancellation announcement from them...
BTW, AMD hasn't yet stated a full roadmap for 2008...but they do hint at a change in architecture.

"As a result, AMD expects to increase the performance-per-watt of today?s AMD Opteron? processor-powered servers by approximately 60 percent through 2007, and by approximately 150 percent through 2008"
AMD PR

 

[imported_Questar]

Originally posted by: Viditor

Originally posted by: Questar

Are you saying it takes AMD 5 years to develop a CPU? If that's the case, then my argument still stands, as you know as well as I do that K9 was cancelled in 2003. There is not a new architecture on the AMD road maps through 2008. Also, it puts AMD in a world of hurt since Intel is on a four year schedule.

It takes both Intel and AMD approximately 5 years to develop a CPU. As to K9, I never have seen a cancellation announcement from them...
BTW, AMD hasn't yet stated a full roadmap for 2008...but they do hint at a change in architecture.

"As a result, AMD expects to increase the performance-per-watt of today?s AMD Opteron? processor-powered servers by approximately 60 percent through 2007, and by approximately 150 percent through 2008"
AMD PR

Umm, Intel is on a four year cycle.

The slides for the AMD road map through 2008 are available on the net. The only thing in 2008 is another K8 refresh.

 

[dmens]

Originally posted by: Viditor

Originally posted by: dmens

How can you call SMT a "subset" of SMP when, core resources are shared or partitioned, including L* caches, which is contradictory with the definition of symmetric multiprocessing? SMT is opportunistic, SMP is designed to be balanced.

By looking at it functionally...SMP allows for the simultaneous processing of multiple threads at all times, whereas (as you say) SMT does the same thing when the opportunity presents itself.

ok, then smt cannot functionally work on multiple threads at all times because many resources are shared.

 

[Furen]

Originally posted by: Questar
Umm, Intel is on a four year cycle.

The slides for the AMD road map through 2008 are available on the net. The only thing in 2008 is another K8 refresh.

Intel PLANS to be on a four year cycle, since this is a new plan and we haven't finished even one cycle you can't say for sure (though I hope they can stay on track). The K8 refresh (K8L) is scheduled for 2007, mid 2007 is the general consensus. Ruiz did say that AMD would start sampling a "new architecture" by the end of next year for release in 2008, so that could be K9 (or whatever AMD choses to call it) but I can't say for certain. Right now, it looks like the 65nm K8L will be out there to trade blows with the 45nm Penryn (which is supposed to be a die-shrink of Conroe). In 2008 whatever AMD releases will once again trade blows with Nehalem. Looks to me like Intel and AMD, as long as things go as planned for both, will be releasing products within the same time frames. I will say this, though, AMD IS behind right now, and I'd guess the whole socket debacle that started since the K8's launch is to blame, but if AM2 really is forward-compatible with AM3 chips then AMD may avoid having it happen again.

 

[myocardia]

Originally posted by: Furen
I will say this, though, AMD IS behind right now, and I'd guess the whole socket debacle that started since the K8's launch is to blame, but if AM2 really is forward-compatible with AM3 chips then AMD may avoid having it happen again.

The problem with that, though, if I understand your argument, is that AMD is still going to have to design a new socket for the AM3. The whole point of the 3 in AM3 is that it will use DDR3, and even though the AM3 chips will work on an AM2 board, they will have to use DDR2 RAM to do it, which will definitely limit their productivity/efficiency.

 

[Furen]

Originally posted by: myocardia

Originally posted by: Furen
I will say this, though, AMD IS behind right now, and I'd guess the whole socket debacle that started since the K8's launch is to blame, but if AM2 really is forward-compatible with AM3 chips then AMD may avoid having it happen again.

The problem with that, though, if I understand your argument, is that AMD is still going to have to design a new socket for the AM3. The whole point of the 3 in AM3 is that it will use DDR3, and even though the AM3 chips will work on an AM2 board, they will have to use DDR2 RAM to do it, which will definitely limit their productivity/efficiency.

Will it? DDR2 does nothing for the K8, why do you think DDR3 will? Hell, DDR2 does close to nothing for Conroe and that architecture doesn't have the luxury of an integrated memory controller to maximize memory utilization. Power and density are the two great benefits that DDR2 brings but those who really do need that will upgrade early. Regardless, the benefit of having compatible sockets is that motherboards don't suddenly become obsolete. AMD could start making DDR3 K8s tomorrow and they'd still work with DDR2 motherboards so even if the market wasn't ready for DDR3 adoption (ie. if the RAM was too damn expensive) AMD wouldn't have to keep working on its non-DDR3 chips.

 

[intangir]

Originally posted by: Viditor
2. SMT is a subset of SMP (multicore)
3. Huge caches (L3) are being released in mid 2007
4. AMD has never said anything about 10GHz (in fact, that's a fairly silly comment...)

2. No no no. Where to begin? SMT is completely orthogonal to CMP (multicore).

SMT (simultaneous multithreading) is a feature implemented within a single core so it can execute instructions from multiple threads in the same clock cycle. SMP (symmetric multiprocessing) utilizes multiple identical processors in a shared-memory system. CMP (core multiprocessing) is multicore, and is essentially SMP on a single processor die.

Please, do not confuse these terms.

3. 2 MB is huge? Huh. That's about a tenth the L3 cache size on currently shipping processors from Intel. Just sayin'.

4. Well, um, I'll just let the links others posted speak for themselves.

Hate to pick on you, but you offered such an easy target.

 

[Hellotalkie]

Originally posted by: keysplayr2003
Just because Intel hasn't "announced" it, doesn't mean they aren't working on something to steal thunder from AMD's 4x4. Intel likes to be first at everything. Doesn't always work out that way, but that trend has not gone unnoticed. How far off is 4x4 anyways.

EDIT: Just saw. 2H '07. At least 7 months not including the rest of August. Well, hopefully they can speed that up a bit, and when it gets here, I hope it will be awesome.

Which company doesnt like to be first at everything against its competetor?