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Barton

N

Newbie71

Junior Member
If Barton were to have 512 KB of full speed on-die L2 cache connected by a 256 bit data path(as opposed to 256 KB connected by 64 bit data path), SSE2, and a 166 MHZ FSB? How much faster would it be clock for clock? I realize that it will probably be a simple die shrink, except just for arguments sake, what kind of improvements would be seen on a clock for clock basis with those enhancements?

 
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