Look at this crazy thing:
Three PCIe 4.0 x4 M.2 slots
www.tomshardware.com
They must be taking slices off the GPU 16x block for the extra 2 m.2 slots. But then again, there are 3 GPU slots so I'm interested how the breakdown works out. It looks like its going to an odder duck than the Asus B450 Strix board.
The only surprising thing is that the main 16 PCIe Port can bifurcate to 8x/4x/4x. At least according to official AMD slides of previous Chipset generations you need a X series Chipset to allow bifurcation to 8x/8x, and there was no mention of 8x/4x/4x at all (Note that Intel consumer Processors supports both 8x/8x and 8x/4x/4x modes, but only allows doing so on Z series Chipsets only). Keep in mind that Zen itself can do 4x/4x/4x/4x, but I'm not sure if this capability was ever exposed in desktop, as it falls onto the category of "Chipset controlled Processor features". Threadripper can do it. Not sure if someone showcased 8x/4x/4x + x4 on AM4 before.
Basically, think that an AM4 Processor itself with its 24 PCIe Lanes loses 4 as it is the downlink to the Chipset, then it can use the other 20 as 8x/4x/4x + 4x. Sounds like you could have a full sized ATX Motherboard with 4 PCIe 4.0 Slots if you wanted to.
So its the CPUs that can't address more than 16MB. Well, that is going to be a big mess to support then, but it was already going to be a big mess. I think people will appreciate the option nonetheless.
Socketed bios chips would kind of solve this. The manufacturers could even charge for them to mitigate the cost of the extra work. I'm not sure how common those are these days.
Socketed Flash EEPROMs would NOT solve this, because they introduced a multitude of issues with unique Motherboard unit data. UUID, MAC Addresses, UEFI NVRAM, and so on, would be lost if you just swapped chips. There goes your Windows activation, too. Too complicated.
To address 32 MiB and bigger SPI Flash EEPROMs you were supposed to support 4 Byte addressing, which I thought that Zen supported since there were Motherboards with 32 MiB SPI chips in the wild. I suppose that the SPI chips themselves support some form of bank switching so that you can tell them to show either the first 16 MiB or the last 16 MiB of the ROM contents on the 16 MiB addressing window, and the problem seems to be that you may require to work with more than 16 MiB at once. Otherwise you're back to the good old days of DOS and the Expanded Memory/EMS.