I you totally disregard the fact that cache (a lot of it in Fermi) is made up of a lot of transistors packed in a tight space...compared to a eg. a MUL wich consists of a few transistors on a larger area...oh wait...
I guess reality didn't like you very broad (and flawed) generalization :hmm:
Well since Fermi is rumoured to be >500mm, and Cypress is 334mm^2 (according to AT), I make that around 50% more area for Fermi and 50% more transistors, despite them being so tightly packed, as you say.
If AT is wrong (some sites seem to say 384mm^2) then that's a 38% bigger die for Fermi (assuming it's the 530mm^2 sites rumour), and the actual difference in transistor counts is ~39% (since Cypress is over 2billion).
Transistor density between the two seems fairly consistent, and AMD may even have them more tightly packed.
So they have 50% more transistors, or 50% more die space before they equal NV's design.
Or it might be 40/40.
So, what was your point?
Also why are you even commenting? The point was that NV are making a larger die with more transistors than AMD on the same process, which means AMD have some headroom to work with.
This thread is about a future product being made on the same process as the current one.
My point was that AMD have headroom because we can already see a larger die being made on the same process. It doesn't matter the specifics of that die, for the most part, just that it's being made.
Basically the fact that NV are already making a larger die means it should be possible to AMD to make a larger die too, thus giving them headroom to improve performance through features (rather than just clocks) despite still being on 40nm.
It has nothing to do with how NV have designed their chip or how much exact room they have, just that they could make a bigger die, quite substantially so in % terms, than they currently have, despite being on the same process.