Wow, you're really asking for a lot... well, here goes nothing.
130nm chips:
Clawhammer: The initial AMD64 core. 1MB cache.
Newcastle: The "successor" to clawhammer. 512K cache. It was adopted by AMD because the die size is smaller ~25% than a comparable clawhammer, which helped yield-wise. They generally overclock better than clawhammers since they run slightly cooler.
Paris: Sempron (that's all I have to say).
The 130nm chips are mostly based on the C core revision (I think)
90nm Chips (s939):
Winchester: The first 90nm shrink. It had a better memory controller than C revision cores but was mostly just a die shrink. Runs a hell of a lot cooler than any 130nm chip but isnt the greatest overclocker out there. 512K cache.
Venice: The current E stepping core. It runs cool, overclocks pretty well, has an improved memory controller, SSE3, Dual Stress Layer. 512K cache.
San Diego: Same as Venice, but with 1MB cache. Generally better overclockers.
Manchester: Dual-core. 512K cache per core. Includes SOME X2 3800s, 4200s and 4600s. E4 stepping, I think.
Toledo: Dual-Core. 1MB cache per core. Includes 4400s and 4800s. Some cache-disabled toledos end up being 3800s, 4200s and 4600s. E6 stepping.
90nm Semprons (s754)
Palermo: Some are D stepping, some are E stepping. E stepping Palermos have SSE3 and an improved memory controller. D stepping Palermos are the winchester equivalents. Either 128K or 256K cache.
Mobile 90nm (s754)
Newark: Mobile Athlon 64. 1MB cache. 63W TDP (I think). Very good overclockers according to what I've heard. Should be an E revision core.
Lancaster: Turion 64. Either 1MB or 512K cache. Either 35W or 25W TDP. I know very little about them and what I know may be wrong. They should be E revision cores. I've heard that they're actually made to be mobile, they're not just binned for lower power consumption. Because of this they're not great overclockers. They do run pretty cool and all, but they're not stable at high clock speeds.
Please be aware that when I say "cache" I mean L2 cache. All these CPUs have 64K instruction + 64K data L1 caches.
As you should know (shame on you if you dont) socket 754 K8s have a single-channel DDR controller on die, while socket 939 K8s have a dual-channel DDR controller.