As much as I wanted a Haswell rig, now I'm thinking twice about it.

[Galatian]

Performance preview
http://www.tomshardware.com/reviews/core-i7-4770k-haswell-performance,3461.html

Very disappointing: no TSX for K processors and I was hoping for higher memory clocks supported...I might just go with Ivy-E then.

 

[MisterMac]

Who now believes Steamroller (If ever released as a AM type socket ) will actually have 20% IPC increase?


It's tom's - so i'll wait final silicon and more leaks\real reviews - but damn it's disappointing.


Seems like the way forward really isn't increased IPC.
But maybe a hardware based solution to the thread problems of software.

I don't have confidence software will ever truly efficiently at some point solve the the many thread problems mainstream wise.

 

[inf64]

Who now believes Steamroller (If ever released as a AM type socket ) will actually have 20% IPC increase?


It's tom's - so i'll wait final silicon and more leaks\real reviews - but damn it's disappointing.


Seems like the way forward really isn't increased IPC.
But maybe a hardware based solution to the thread problems of software.

I don't have confidence software will ever truly efficiently at some point solve the the many thread problems mainstream wise.

SR? I don't think even AMD knows how much faster it will be . I kid I kid, but seriously it's pretty much unknown.

As for THG, their previous previews very pretty much spot on. I doubt there is any magic pixie dust to make Haswell perform much better than this. The only thing that comes to mind is that it might have more tweaked Turbo so it can stay longer at higher clocks(if temperature is adequate). I doubt you will see "more ipc" from final silicon.
What you will see is much better performance if workloads start to support AVX2 or FMA3. Looking at previous ISA additions and their implementation in software,it can be a long wait(maybe 1-3 years for it to become somewhat present in the common desktop apps).

 

[Genx87]

I am having a hard time getting excited about upgrading anything in my computer. i2500k+GTX 470 rocks every game I play.

 

[Ajay]

+1.

Only thing I'd like to see in HW desktop parts is their ability to OC well without high volts, and if they get rid of the frog snot TIM on their K parts.

Yep. Plus, the only big gains are going to be on recompiled or new apps. I expect we'll see some nice gains in CPU physics on updated gaming engines.

TSX' main advantage will be on the server side when the number of threads is >> than the number of cores.

 

[ShintaiDK]

Yep. Plus, the only big gains are going to be on recompiled or new apps. I expect we'll see some nice gains in CPU physics on updated gaming engines.

TSX' main advantage will be on the server side when the number of threads is >> than the number of cores.

Not as such.

TSX targets a certain class of shared-memory multi-threaded applications; specifically multi-threaded applications that actively share data.

TSX however is a hyped term it seems.

 

[Homeles]

Who now believes Steamroller (If ever released as a AM type socket ) will actually have 20% IPC increase?

The changes are absolutely there to hit a 20% IPC increase. AMD's claim was actually 30%, FYI. Go read up on it: http://www.brightsideofnews.com/new...core-architectural-enhancements-unveiled.aspx

IPC won't be the problem -- it's clock speed that will be the issue.

As for Haswell: Shame about TSX. I'm hopeful that we won't need to buy a K series processor to overclock, though. The important information was left out -- Haswell's performance was in line with expectations; no surprise there. But what about power consumption? How well will it overclock? Those people that grab Ivy Bridge instead will be eating their hats if Haswell hits 5.5GHz. At the very least, we should be able to expect more chips consistently hitting the magic 5.0. It's too early to draw conclusions, though -- too many unknowns right now.

 

[Meekers]

The way I see it Intel just gave AMD 2 free generations to catch up on overall performance. If steamroller can realize a 20%+ IPC increase things might get interesting again.

 

[Ajay]

Not as such.


TSX however is a hyped term it seems.

Uh, yeah, larger enterprise level application software often uses more threads than CPU cores. Heck, I've written embedded and Desktop applications that use more threads than CPU cores.

And TSX isn't hyped, of course it isn't a 'cure all' as some have hyped, but that's not Intel's fault, IMO.

A simple example: http://software.intel.com/en-us/blo...s-and-transactional-synchronization-explained

 

[Ajay]

The way I see it Intel just gave AMD 2 free generations to catch up on overall performance. If steamroller can realize a 20%+ IPC increase things might get interesting again.

AMD better hit their own +30% IPC increase if they want a significant net performance gain for Kaveri. As alluded to by Homes, there are rumors about that 28nm Bulk Si will hit clocks speeds of 10-20% less than 32nm SOI (Piledriver); which makes sense since the point of SOI was hitting higher clock speeds than Bulk).

 

[Homeles]

My comment wasn't so much about the process tech, but that is a part. There are just a lot of power-hungry, yet huge performance boosting design decisions going into Steamroller -- first of which is the doubled decode width. The uop cache should help, along with the dynamic L2, but how they'll manage to maintain clock speed while tackling everything else is beyond me. Thankfully GloFo's 28nm library is reportedly very similar to their 32nm library, so hopefully AMD will run into less issues this time around. But I mean come on, 30% is a lot. That puts AMD back in the game, and then some. 30% IPC is certainly doable, but can we really expect clock speeds to stay the same?

 

[Ajay]

My comment wasn't so much about the process tech, but that is a part. There are just a lot of power-hungry, yet huge performance boosting design decisions going into Steamroller -- first of which is the doubled decode width. The uop cache should help, along with the dynamic L2, but how they'll manage to maintain clock speed while tackling everything else is beyond me. Thankfully GloFo's 28nm library is reportedly very similar to their 32nm library, so hopefully AMD will run into less issues this time around. But I mean come on, 30% is a lot. That puts AMD back in the game, and then some. 30% IPC is certainly doable, but can we really expect clock speeds to stay the same?

I don't think we can expect clock speeds to stay the same just based on the process change alone. But, you make some good points about the architecture possibly slowing down the clock rates as well. I'm expecting a net ~15% performance gain/watt - just as AMD's old roadmap shows. I hope they make it just for the sake of improved consumer choice.

Anyone know what the expected GPU performance jump is expected to be from Trinity to Kaveri?

 

[Homeles]

Should be pretty good with the GDDR5.

 

[ShintaiDK]

The changes are absolutely there to hit a 20% IPC increase. AMD's claim was actually 30%, FYI. Go read up on it: http://www.brightsideofnews.com/new...core-architectural-enhancements-unveiled.aspx

IPC won't be the problem -- it's clock speed that will be the issue.

As for Haswell: Shame about TSX. I'm hopeful that we won't need to buy a K series processor to overclock, though. The important information was left out -- Haswell's performance was in line with expectations; no surprise there. But what about power consumption? How well will it overclock? Those people that grab Ivy Bridge instead will be eating their hats if Haswell hits 5.5GHz. At the very least, we should be able to expect more chips consistently hitting the magic 5.0. It's too early to draw conclusions, though -- too many unknowns right now.

AMD didnt say 30% IPC on the entire core. Its simply 30% faster decode on the frontend. And its based purely on simulation. So lets not hype it.

 

[ShintaiDK]

The way I see it Intel just gave AMD 2 free generations to catch up on overall performance. If steamroller can realize a 20%+ IPC increase things might get interesting again.

I think you forget the performance/watt part.

Currently AMDs CPUs run out of spec because they cant keep the power consumption under control.

 

[Homeles]

AMD didnt say 30% IPC on the entire core. Its simply 30% faster decode on the frontend. And its based purely on simulation. So lets not hype it.

Uh, they doubled the decode width from 4 ops per cycle to 8. That's not hyping anything -- it's fact. And this slide is pretty clear about the 30% claim:

http://images.anandtech.com/doci/6201/Screen Shot 2012-08-28 at 4.38.09 PM.png

"Hyping" Steamroller is the absolute last thing that I'm doing. I've made my doubts about clock speed abundantly clear.

 

[IntelUser2000]

Uh, they doubled the decode width from 4 ops per cycle to 8. That's not hyping anything -- it's fact. And this slide is pretty clear about the 30% claim:

http://images.anandtech.com/doci/6201/Screen Shot 2012-08-28 at 4.38.09 PM.png

"Hyping" Steamroller is the absolute last thing that I'm doing. I've made my doubts about clock speed abundantly clear.

But I believe its marketing play when that slide is saying "30% OPs per cycle improvement" rather than saying "30% performance per cycle improvement".

How do you quantify individual improvements without being the head engineer of the design?

And the hype part is believing 30% on a unconfirmed leak versus 15% on official claims. How many times have we been disappointed even with "official figures"? AMD isn't alone of course. Intel, and others in the CPU industry does the same as well.

 

[inf64]

The problem is that although the performance(per clock) might improve by 30% in those workloads AMD lists in footnote, clock speed as Homeless said might drop by ~15%. This would in turn mean that overall performance improvement over PD core will be in line with that graph they gave back in 2011(10-15% perf. jumps per year).

 

[Rifter]

I was going to go haswell on release but have noe re-evaluated my situation.

Now i am going to do a GPU upgrade soon and then wait out second stepping haswell chipset to avoid USB3 bug so will probably upgrade to haswell late this year or early next.

 

[Homeles]

But I believe its marketing play when that slide is saying "30% OPs per cycle improvement" rather than saying "30% performance per cycle improvement".

How do you quantify individual improvements without being the head engineer of the design?

And the hype part is believing 30% on a unconfirmed leak versus 15% on official claims. How many times have we been disappointed even with "official figures"? AMD isn't alone of course. Intel, and others in the CPU industry does the same as well.

They've listed the changes that are coming, and they're substantial. If you take a look at this article, it highlights the biggest weaknesses of Bulldozer. Piledriver addressed one of them (clock speed), and Steamroller will address the other two (branch misprediction penalty and L1 instruction cache). Plus, we're getting double the decode width.

AMD's taking IPC to the moon with SR. These CMT cores will be virtually indistinguishable from typical ones. I just don't know how they're going to implement all of this while staying within the same thermal headroom. And it's AMD after all -- it's better for my well being and sanity if I chalk things up to being a letdown before they release. With Intel, if they say they're shooting for the moon, I'll expect them to make it there, or at least get close.

 

[shady28]

as much as the performance increase is not impressive in many of the things they tested,

this was good

and they didn't include power usage tests.

That is only a 14% bump from IB to Haswell. And yes, that's about the best increase they got.

 

[VirtualLarry]

Thinking of going with 8/10-core IB-E, and this mobo, ASRock 2011 Extreme6
http://www.newegg.com/Product/Produc...82E16813157289

64GB of DDR3-1600 or 1866 (2133?), Win7 Pro, would make a decent workstation for the near future.

 

[ehume]

Waiting to see the OC potential of Haswell. If it has the gunk between the cpu and the ihs, I'll just get the IB in June. If OTOH it has solder, HW will be worth waiting for the kinks to get worked out, say October.

Gotta wait to see.

 

[ShintaiDK]

Uh, they doubled the decode width from 4 ops per cycle to 8. That's not hyping anything -- it's fact. And this slide is pretty clear about the 30% claim:

http://images.anandtech.com/doci/6201/Screen Shot 2012-08-28 at 4.38.09 PM.png

"Hyping" Steamroller is the absolute last thing that I'm doing. I've made my doubts about clock speed abundantly clear.

Decode yes, execution no. So please refrain from using IPC when its not the case.

 

[Vesku]

They've listed the changes that are coming, and they're substantial. If you take a look at this article, it highlights the biggest weaknesses of Bulldozer. Piledriver addressed one of them (clock speed), and Steamroller will address the other two (branch misprediction penalty and L1 instruction cache). Plus, we're getting double the decode width.

AMD's taking IPC to the moon with SR. These CMT cores will be virtually indistinguishable from typical ones. I just don't know how they're going to implement all of this while staying within the same thermal headroom. And it's AMD after all -- it's better for my well being and sanity if I chalk things up to being a letdown before they release. With Intel, if they say they're shooting for the moon, I'll expect them to make it there, or at least get close.

Yeah, best not to try to predict anything. Can't even be sure we'll see 4-5 module AM3+ Steamroller or not. Though there is potential.