[Ars] AMD confirms high-end Polaris GPU will be released in 2016

[AtenRa]

Yeah, that would seem more reasonable. We've seen P10 at 850MHz competing against a stock 950, though it's unknown what the GPU utilization was under vsync for both those cards. Hard to say whether it will scale the significant amount it would need to to move from competing with a 950 to competing with a stock 380, but it doesn't seem unlikely that the demo P10 was tuned down quite a bit to maximize the efficiency for demo purposes and there might be decent bit more power on tap.

I think raghu is completely out to lunch on it hitting 380 levels @ 50W though.

The demo Polaris 10 could be a cut off die (not full Polaris 10) 😉

 

[MrTeal]

The demo Polaris 10 could be a cut off die (not full Polaris 10) 😉

Could be. There's no reason to think that since it would be counter-productive to their aims in that test, but maybe they had issues where they couldn't show a full die.

Too bad Ian never commented on how many GDDR5 modules the card used in the demo had, assuming they got to see the PCB. It would have been nice to know if it had four or eight GDDR5 modules. 🙂

 

[MrTeal]

Remember the 1.25Ghz Fiji from that site 😉

And 3GB for 2048bit HBM also sounds odd.

Unfortunatelly I can't.


There was one guy, called Cloudfiresomething. You should have seen how he was hyping the Maxwell on Notebookreview forum. That was good laugh.

That's because the Sandra results describe crazy and entirely wrong configurations. For instance, when I run the bench Sandra 2016 describes my config as 2X R200 series with 8GB DDR3 on a 512-bit bus.

 

[raghu78]

Could be. There's no reason to think that since it would be counter-productive to their aims in that test, but maybe they had issues where they couldn't show a full die.

Too bad Ian never commented on how many GDDR5 modules the card used in the demo had, assuming they got to see the PCB. It would have been nice to know if it had four or eight GDDR5 modules. 🙂

http://techreport.com/news/27676/samsung-starts-making-8gb-gddr5-memory-chips

With the availability of 8 Gbit GDDR5 chips almost a year back we can have 4 GB capacity with a 128 bit GDDR5 memory bus. The PS4 uses just 8 chips to achieve 8 GB capacity on a 256 bit GDDR5 memory bus. I would like to see 4GB as the default configuration on full Polaris 10.

 

[Glo.]

That's because the Sandra results describe crazy and entirely wrong configurations. For instance, when I run the bench Sandra 2016 describes my config as 2X R200 series with 8GB DDR3 on a 512-bit bus.

I have already addressed that with my another post on the topic.
http://forums.anandtech.com/showpost.php?p=38033692&postcount=396
2048 Bit ,3 GB RAM.

With 2 GB stacks, you would have 2 cubes, both 1024 bit one would be 2 GB and second would 1 GB.

 

[MrTeal]

I have already addressed that with my another post on the topic.
http://forums.anandtech.com/showpost.php?p=38033692&postcount=396
2048 Bit ,3 GB RAM.

With 2 GB stacks, you would have 2 cubes, both 1024 bit one would be 2 GB and second would 1 GB.

Umm, that doesn't explain it at all. Why then do my 290s show a 512-bit DDR3 bus, official user CAS shows a 290X with 3GB DDR5, R9 Fury X (or Nano) shows 3GB DDR5 @ 2GHz on a 2048-bit bus, and R9 Fury shows 3GB of no type specified on a 500MHz 4096-bit bus.

If you look at the high cryptography list sorted by performance, none of those AMD results are valid configurations.

 

[MrTeal]

http://techreport.com/news/27676/samsung-starts-making-8gb-gddr5-memory-chips

With the availability of 8 Gbit GDDR5 chips almost a year back we can have 4 GB capacity with a 128 bit GDDR5 memory bus. The PS4 uses just 8 chips to achieve 8 GB capacity on a 256 bit GDDR5 memory bus. I would like to see 4GB as the default configuration on full Polaris 10.

Not sure what capacity has to do with it, though I'd agree that 4GB is likely to be the default full chip config. It would be interesting to see because 4 chips would imply a 128-bit bus, while eight chips would almost certainly be a 256-bit bus.

 

[Glo.]

Umm, that doesn't explain it at all. Why then do my 290s show a 512-bit DDR3 bus, official user CAS shows a 290X with 3GB DDR5, R9 Fury X (or Nano) shows 3GB DDR5 @ 2GHz on a 2048-bit bus, and R9 Fury shows 3GB of no type specified on a 500MHz 4096-bit bus.

If you look at the high cryptography list sorted by performance, none of those AMD results are valid configurations.

All I say is that it is completely possible to make 3 GB HBM2 GPU with 2 stacks of RAM.

 

[MrTeal]

All I say is that it is completely possible to make 3 GB HBM2 GPU with 2 stacks of RAM.

You could, but it would be a very sub-optimal arrangement, akin to when nVidia put out the 660Ti. Given that every single other description of an AMD GPU's memory bus is wrong though, wouldn't the much, much more likely explanation be that the listed configuration is just wrong and has nothing at all to do with Polaris?

 

[Glo.]

As I said, it could be engineering sample only, and only for experimental purposes.

 

[MrTeal]

As I said, it could be engineering sample only, and only for experimental purposes.

They could have created such a beast, you're right. We'll have to agree to disagree on this one though. Specifically I would say that these three results from my image above, including the one you're talking about, are all from the same guy on the same day. One of them is labeled 2xFury with the exact same memory config as the one you're discussing, and given that Sandra describes nothing correctly I would further say the he just has a couple Fury X's and has nothing at all to do with Polaris 11.

Please, continue to be on the hype train with everything falling in line perfectly though. 😛

 

[raghu78]

Not sure what capacity has to do with it, though I'd agree that 4GB is likely to be the default full chip config. It would be interesting to see because 4 chips would imply a 128-bit bus, while eight chips would almost certainly be a 256-bit bus.

http://www.anandtech.com/show/9886/amd-reveals-polaris-gpu-architecture

"In any case, the GPU RTG showed off was a small GPU. And while Raja’s hand is hardly a scientifically accurate basis for size comparisons, if I had to guess I would wager it’s a bit smaller than RTG’s 28nm Cape Verde GPU or NVIDIA’s GK107 GPU, which is to say that it’s likely smaller than 120mm2. This is clearly meant to be RTG’s low-end GPU, and given the evolving state of FinFET yields, I wouldn’t be surprised if this was the very first GPU design they got back from Global Foundries as its size makes it comparable to current high-end FinFET-based SoCs. In that case, it could very well also be that it will be the first GPU we see in mid-2016, though that’s just supposition on my part."

The Polaris chip demoed at CES was smaller than GK107 (118 sq mm) and Cape Verde(123 sq mm). I would guess its a 110 sq mm chip. Such a tiny chip means we are looking at a 128 bit GDDR5 memory bus. A 256 bit memory controller cannot be fit on such a small chip as it does not have the area for I/O pads for a 256 bit GDDR5 bus.

 

[MrTeal]

http://www.anandtech.com/show/9886/amd-reveals-polaris-gpu-architecture
The Polaris chip demoed at CES was smaller than GK107 (118 sq mm) and Cape Verde(123 sq mm). I would guess its a 110 sq mm chip. Such a tiny chip means we are looking at a 128 bit GDDR5 memory bus. A 256 bit memory controller cannot be fit on such a small chip as it does not have the area for I/O pads for a 256 bit GDDR5 bus.

Que? Source for that rather dubious statement, please?

Edit: Not the statement that it won't have a 256-bit bus of course. Just the one that it's physically impossible to fit more than the couple hundred pads you need for a 128-bit GDDR5 bus.

 

[Head1985]

You forget some new posters claimed that Fury X will be 40% faster then Titan X and they diapered after Fury X release. Lack of hype control from AMD.

well fury X should be alot faster than TITANX.But AMD fuck up design with only 4x pipeline and 64rops.
On paper fury X should be like 20% faster than TITANX.
But in reality because same front end from hawaii with 4x pipelines its not much faster than 2800SP 390x despite it have 4100SP.

 

[raghu78]

Que? Source for that rather dubious statement, please?

Edit: Not the statement that it won't have a 256-bit bus of course. Just the one that it's physically impossible to fit more than the couple hundred pads you need for a 128-bit GDDR5 bus.

Can you point out a single GPU in the last 8 years since GDDR5 launched which had a 110-120 sq mm GPU with a 256 bit GDDR5 bus. 😀

To give you an idea of GPU layout here are pics of Tahiti, Pitcairn and Cape Verde

http://www.anandtech.com/show/6210/amd-southern-islands-gpu-die-shots-released

btw the reason for these tiny GPUs (100-120 sq mm) to have 128 bit memory bus is also size and cost. Smaller memory bus translates to smaller boards with lesser number of PCB layers which makes them cheap to produce.

 

[Silverforce11]

Don't bother entertaining the possibility such a small chip like Polaris 10 to have a 256 bit bus, that goes against logic of designing efficient and cost effective chips for the LOW-END segment.

Regardless, it doesn't need it. Faster GDDR5 + 128 bit bus + next-gen bandwidth compression = more than enough for 380 class performance.

 

[raghu78]

Don't bother entertaining the possibility such a small chip like Polaris 10 to have a 256 bit bus, that goes against logic of designing efficient and cost effective chips for the LOW-END segment.

Regardless, it doesn't need it. Faster GDDR5 + 128 bit bus + next-gen bandwidth compression = more than enough for 380 class performance.

exactly. :thumbsup:

 

[iiiankiii]

well fury X should be alot faster than TITANX.But AMD fuck up design with only 4x pipeline and 64rops.
On paper fury X should be like 20% faster than TITANX.
But in reality because same front end from hawaii with 4x pipelines its not much faster than 2800SP 390x despite it have 4100SP.

I agree. It shocked the heck out of me when the Fury X was trading blows with a 390x at 1080 and 1440. I couldn't believe how badly AMD scrwed it up. The specs didn't add up at all.

 

[Azix]

is it confirmed polaris 10 is GDDR5? because such a small chip with one or 2 stacks of HBM would be really good. Especially in laptops. No need for stacks on the PCB, traces on the PCB. Could be ridiculously tiny board for desktop.

Would be waste building it for gddr5

 

[MrTeal]

Can you point out a single GPU in the last 8 years since GDDR5 launched which had a 110-120 sq mm GPU with a 256 bit GDDR5 bus. 😀

To give you an idea of GPU layout here are pics of Tahiti, Pitcairn and Cape Verde

http://www.anandtech.com/show/6210/amd-southern-islands-gpu-die-shots-released

btw the reason for these tiny GPUs (100-120 sq mm) to have 128 bit memory bus is also size and cost. Smaller memory bus translates to smaller boards with lesser number of PCB layers which makes them cheap to produce.

That's not at all what I asked. There are of course reasons to not use a larger memory controller in a small GPU, and thus far no GPU in that size range would have needed one. Chances are we won't see one here either, though if AMD sticks with 7Gbps GDDR5 for cost/time line constraints it could be a limitation if the chip does end being as powerful as you suggest. Tonga levels of performance under a 112GB/s 128-bit bus would require much improved compression techniques; it would be an interesting data point to have while we wait.

What I asked you to provide a source for was your statement that you can't fit more than a 128 bit bus into a 100mm chip because the IO pads are just too large. GDDR5 has 67 signal pins, so adding two or four chips isn't a huge number more signals on the die. It's not inconsequential of course, but with even traditional solder bump attachment to the substrate offering 150um or 130um pitch and copper pillar die attach offer even greater density, there doesn't seem to be a physical limit that would prevent it. If I am missing some engineering aspect of it that would prevent it I'd love to see it, but it really sounds like you just made up that limitation off the top of your head because it sounded good, without any real evidence as to whether its true or not.

 

[MrTeal]

is it confirmed polaris 10 is GDDR5? because such a small chip with one or 2 stacks of HBM would be really good. Especially in laptops. No need for stacks on the PCB, traces on the PCB. Could be ridiculously tiny board for desktop.

Would be waste building it for gddr5

Raja held up an unsoldered GPU for the press to see, and no one mentioned that it was an HBM on interposer design.

 

[Azix]

Raja held up an unsoldered GPU for the press to see, and no one mentioned that it was an HBM on interposer design.

Hmm. that would suggest gddr5 since hbm would be visible on the package that goes on the PCB, but maybe that was GPU without interposer and HBM

 

[3DVagabond]

It could have been a raw chip too.

 

[JDG1980]

The Polaris chip demoed at CES was smaller than GK107 (118 sq mm) and Cape Verde(123 sq mm). I would guess its a 110 sq mm chip. Such a tiny chip means we are looking at a 128 bit GDDR5 memory bus. A 256 bit memory controller cannot be fit on such a small chip as it does not have the area for I/O pads for a 256 bit GDDR5 bus.

One possibility is that it could have a memory controller designed to work with either GDDR5 or GDDR5X. Parts that are low-end, or ultra-low-power would be designed to use standard GDDR5 at lower core clocks, while the 75W desktop card would use GDDR5X and higher core and memory clocks to allow the chip to stretch its legs.

We've seen dual memory controllers in the past, especially on small chips; Cape Verde works with both DDR3 and GDDR5, for instance. And GDDR5X is supposed to be a relatively simple addition to the GDDR5 standard, this shouldn't cost much extra die space.

Even 1st generation GDDR5X is supposed to have 12 Gbps data rates (eventual target is 16 Gbps, and Micron claims to have hit 13 already). A 128-bit bus with 12 Gbps GDDR5X would provide 192 GB/sec of memory bandwidth, which is more than the current Tonga cards have on tap.

Micron says mass production of GDDR5X starts this summer. If Apple needs Polaris 10 sooner for the MacBook Pro refresh, standard GDDR5 would still let the chip offer unparalleled performance per watt, and slower core clock rates would make a memory bandwidth bottleneck less of an issue.

 

[maddie]

There are options between 128 bit and 256 bit for the memory bus. A bit better memory compression with a 192 bit bus allowing 3GB & 6 GB for the slowest new cards.