ARM and Intel team up for 10nm

[carop]

Not true, see links below.

http://www.cerc.utexas.edu/utda/publications/C111.pdf

Wiki:

https://en.wikipedia.org/wiki/Multiple_patterning#Published_approaches

The half-pitch (HP) is defined by the Rayleigh Resolution Equation. The smallest HP that can be printed in single exposure is 36 nm. However, a k1 process factor of 0.25 is considered to be a very difficult, if not impossible, process. Today's best processes have k1 = 0.28. So, the practical half pitch is about 38 - 40 nm.

Here is a slide from IMEC that shows the (practical) limits of various multiple patterning techniques:

45nm 193i LE3 (used by Samsung N10 process)

40nm 193i SADP (used by Intel and TSMC N10 processes)

28nm EUV single exposure (See Toshiba slide for explanation)

20nm 193i SAQP

 

[SAAA]

Wasn't there some info about using self-aligned triple pattering for some steps in Intel's 14nm? Also I don't get what's the problem with sub-40nm details if the fin of the fets is already 8-10nm wide at best?

Anyway I'm still impressed by their claim of better than 0.5x scaling, it almost makes up for the longer time between nodes: we were used to 2 and now it's more than 3 years per generation...
Looking at actual Broadwell parts real scaling is around 2x when all the previous steps got 1.6-1.7x to the previous gen, if they keep up that over 10nm in 6 years it's almost the same as going for three smaller increases. It also fits nicely with the 3 years process-arch-optimization model, there goes the tick-tock from the door and it comes back by the window.