ARM and Intel team up for 10nm

[NTMBK]

http://techreport.com/news/30530/arm-and-intel-team-up-to-ease-custom-10-nm-finfet-development

 

[Phynaz]

Beat me to it!

http://www.eetimes.com/document.asp?doc_id=1330311

"Separately, China’s Spreadtum will make mobile chips in Intel’s current 14nm process. In addition, Intel’s 14nm Stratix 10 FPGAs will sample next quarter using a novel packaging technology that provides a lower cost than existing 2.5D techniques."

 

[Nothingness]

Good to see Intel getting serious about foundry business. I guess it also reinforces the fact Atom is dead for mobile platforms.

 

[Arachnotronic]

Good to see Intel getting serious about foundry business. I guess it also reinforces the fact Atom is dead for mobile platforms.

Atom for mobile was just not a good product. It will not be missed.

 

[witeken]

Best / coolest semiconductor news of the year, but I don't think it will be very major because switching foundries isn't all that easy or something that gets done overnight. Just look at Altera. Announced many years ago, still no 14nm products. Long term it could be interesting to see what happens.

And 54nm pitch! For comparison: http://images.anandtech.com/doci/8367/14nmFeatureSize.png.

That's in line, about the same improvement as 14nm. So Intel's done it again! 10nm is a real full node shrink again. Now we need the interconnect pitch...

 

[Arachnotronic]

Best / coolest semiconductor news of the year, but I don't think it will be very major because switching foundries isn't all that easy or something that gets done overnight. Just look at Altera. Announced many years ago, still no 14nm products. Long term it could be interesting to see what happens.

And 54nm pitch! For comparison: http://images.anandtech.com/doci/8367/14nmFeatureSize.png.

That's in line, about the same improvement as 14nm. So Intel's done it again! 10nm is a real full node shrink again. Now we need the interconnect pitch...

You can derive interconnect pitch from the other slide that Intel has in the deck claiming 0.46x shrink from 14nm.

(0.46*3640)/54 ~= 31nm.

 

[witeken]

You can derive interconnect pitch from the other slide that Intel has in the deck claiming 0.46x shrink from 14nm.

(0.46*3640)/54 ~= 31nm.

You mean this slide?

0.46x is just crazy! But it isn't placed at the 10nm, so just general, which is strange because even 14nm wasn't 0.46x.

Great job if true. Only problem is the [meh] TTM. Doubt we'll see much 10nm before 2018...

Tech's become quite boring in the last few years.

 

[dark zero]

Wait... Isn't Softbank the one who allowed it? I mean.... ARM itself wouldn't accept a deal like that due competition, but now that is Softbank the one.... I won't be surprised if Intel in some years buys ARM for real.

 

[trivik12]

IDF used to be awesome. Now they are just meh. The conroe one in 2006 is still the best one yet. Sadly the CPU market is no longer interesting.

But I am curious that intel did not go for Apple's fab business. That would have been a great revenue generator. may be intel would go for A12 in 2018.

 

[hrga225]

Good to see Intel getting serious about foundry business.

I am not so sure about this.This could just be for their Altera part of business.

 

[Nothingness]

I am not so sure about this.This could just be for their Altera part of business.

It's for LG Electronics...

 

[hrga225]

It's for LG Electronics...

Really?Got some link?I'm really interested what's that about.

 

[Nothingness]

Really?Got some link?I'm really interested what's that about.

Educated guess based on this:
https://newsroom.intel.com/editorials/accelerating-foundry-innovation-smart-connected-world/

Our 10 nm design platform for foundry customers will now offer access to ARM® Artisan® physical IP, including POP™ IP, based on the most advanced ARM cores and Cortex series processors. Optimizing this technology for Intel’s 10 nm process means that foundry customers can take advantage of the IP to achieve best-in-class PPA (power, performance, area) for power-efficient, high-performance implementations of their designs for mobile, IoT and other consumer applications.

They talk about foundry customers, which Altera is not anymore

They further add:

LG Electronics will produce a world-class mobile platform based on Intel Custom Foundry’s 10 nm design platform. We’re pleased to welcome them as a customer.

As far as I know LG Electronics is using ARM cores.

So yes, guesses, but I'm confident I'm correctly guessing

 

[Sweepr]

Will be interesting to compare Samsung, Qualcomm and LG high-end ARM SoCs from now on - different foundries.

 

[hrga225]

Educated guess based on this:
https://newsroom.intel.com/editorials/accelerating-foundry-innovation-smart-connected-world/

They talk about foundry customers, which Altera is not anymore

They further add:

As far as I know LG Electronics is using ARM cores.

So yes, guesses, but I'm confident I'm correctly guessing

Thank you!
2019 will be interesting for fab comparisons!

 

[FIVR]

Have they finally succeeded in Fabbing Altera FPGAs on their bunk 14nm node? They set out to do that in 2014 and I have yet to see integrated Xeons or even just normal 14nm FPGAs. Meanwhile, Xilinx is producing 14nm FPGAs with ARM CPUs and continues to control the majority of the market.

It is too bad how much incentive CEOs have to allow acquisitions by large, less than reputable companies that may just be benefiting from a lack of competition and shady business practices... such acquisitions serve neither the large companies with slave markets nor the innovative smaller companies like Altera who end up being under new dysfunctional management. Had Altera partnered with samsung or qualcomm/TSMC instead of being gobbled up by the lumbering neurosis of Intel's "innovation" they would have a competitive product.

 

[DrMrLordX]

What makes you think Intel's 14nm node is "bunk"?

 

[witeken]

When will we see what that 14nm+ means? What changes were made?

 

[jpiniero]

When will we see what that 14nm+ means? What changes were made?

Probably closer to when Coffee Lake comes out; but I doubt there is much there other than they optimized the node a bit more.

 

[SAAA]

When will we see what that 14nm+ means? What changes were made?

Check out the Skylake thread: https://forums.anandtech.com/threads/intel-skylake-thread.2428363/page-297

12% better performance, turns out to be a 200MHz clock bump on all the line of processors. Also there might be some tuning to get even higher clocks at the high end because Kabylake-S reaches 4.5GHz and Kabylake-X might push to almost 5 at stock if the wattage is any indication.

14nm started bad but yields are becoming good and clocks too, I can't wait to see what 10nm brings to the table...

 

[witeken]

Interview with Mark Bohr on 10nm! Not a whole lot new information, but nice to hear his words.

Deeper Inside Intel: http://semiengineering.com/deeper-inside-intel/

SE: Intel recently announced its 10nm finFET technology. Can you describe the process?

Bohr: Regarding some of those process details, we’ll keep them close to our vest a little while longer. We did disclose some relevant data, the first of which is gate pitch. It’s a very key factor in scaling for both logic and memory. We showed another metric of gate pitch times logic cell height. So we disclosed enough to make the point that our 10nm technology is a big step forward, better than the usual 0.56x area scaling.

SE: What’s different between Intel’s 14nm and 10nm finFET processes?

Bohr: There are always a few changes, but it’s too early to disclose exactly what those changes are. For gate pitch, we’re scaling about 0.76x per generation. But the other design rules are scaling at a faster rate. The result in that area, certainly on 10nm, is much better than the traditional 0.56x area scaling.

SE: When will Intel ship 10nm products?

Bohr: The second half of next year is our plan for volume shipments of our lead 10nm product.

Really nice to hear. I want some yield graphs of both 14nm and 10nm!!

SE: Some foundry vendors will soon ship 10nm finFET processes. Are they ahead or behind Intel?

Bohr: Not all 10nm generations are the same. Others claim they are beginning to ramp their 10nm technology. It’s not the same as our 10nm. It’s almost a full generation behind. Of course, it’s more than two years ago that we ramped up our 14nm, which is more similar to their 10nm. But it’s a little bit hard to compare, at least on this point based on statements.

Now some interesting tidbits:

E: Intel had some past issues with 14nm, forcing it to push out its 14nm process. What did you learn from that experience that you can apply to 10nm?

Bohr: On the top of my head, I can list three. One, we pioneered the use of self-aligned double patterning on 14nm with the knowledge that it’s scalable. The other issue is cycle time through the fab. Every technology generation gets more complex. We have to add more masking steps and other process steps. And if the rate of movement in the fab is the same per step, it will take you longer to complete the flow. We recognized that we didn’t do quite as well on that metric. That’s wafer movement per day in the fab on 14nm. So we’ve been much more aggressive the past two or three years and increased that pace of experimental lots moving through the development fab. And now we’re about 1.6x faster on our 10nm line than we were at a similar timeframe on 14nm.

SE: What else did you learn?

Bohr: On 14nm, we started with a full test chip with all of the metal layers. It just took longer to learn to optimize the transistors. On 10nm, we started with some simpler test chips. We still exercised all of the tight design rules, but this allowed us to make quicker progress on transistors and not have to wait for all of the backend steps to be done.

Further, there's also some talk about beyond 10nm, but to summarize...

Bohr: Exactly what options and features will be chosen for 7nm or 5nm is something I won’t comment on.

 

[carop]

Interview with Mark Bohr on 10nm! Not a whole lot new information, but nice to hear his words.

Deeper Inside Intel: http://semiengineering.com/deeper-inside-intel/

It seems ground rules for N10 processes will look as follows:

Intel N10 process:
Fin Pitch: 32nm
Gate Pitch: 54nm
Metal Pitch: 42nm (1D layout)

Samsung N10 process:
Fin Pitch: 42nm
Gate Pitch: 64nm
Metal Pitch: 48nm (2D layout)

TSMC N10 process:
Fin Pitch: 34nm
Gate Pitch: 64nm
Metal Pitch: 42nm (1D layout)

 

[witeken]

It seems ground rules for N10 processes will look as follows:

Intel N10 process:
Fin Pitch: 32nm
Gate Pitch: 54nm
Metal Pitch: 42nm (1D layout)

Samsung N10 process:
Fin Pitch: 42nm
Gate Pitch: 64nm
Metal Pitch: 48nm (2D layout)

TSMC N10 process:
Fin Pitch: 34nm
Gate Pitch: 64nm
Metal Pitch: 42nm (1D layout)

No. Intel metal pitch would be 31-34nm if they keep their scaling cadence of 14nm, and everything suggests they will. TSMC and Samsung seems about right from what I've gathered.

I have no clue about the fin pitches.

 

[carop]

No. Intel metal pitch would be 31-34nm if they keep their scaling cadence of 14nm, and everything suggests they will. TSMC and Samsung seems about right from what I've gathered.

I have no clue about the fin pitches.

SE: How is Intel dealing with the complexity of the interconnects and other patterning steps?

Bohr: One key innovation that Intel introduced at the 14nm generation, and also scaling and improving upon it at 10nm, is the use of self-aligned double patterning. This is in contrast to the litho-etch-litho-etch that other companies have used. It not only serves us well at 14nm, but it will again on 10nm. Now, I believe other companies have also come around to that line of thought as well.

The smallest feature that can be printed with self-aligned double patterning (SADP) is 40nm.

A metal pitch size of 32-34nm would require self-aligned quadruple patterning (SAQP) or EUV.

The area scaling of 0.46x appears to be achieved using both dimensional (feature size) and functional (design rules) scaling.

 

[Phynaz]

The smallest feature that can be printed with self-aligned double patterning (SADP) is 40nm.

Not true, see links below.

http://www.cerc.utexas.edu/utda/publications/C111.pdf

In this paper, we propose rigorous layout decomposition methods on SADP technique for sub-30nm random shaped logic metal layouts.

Wiki:

https://en.wikipedia.org/wiki/Multiple_patterning#Published_approaches