Are hardware exceptions maskable?

[chrstrbrts]

Hi,

Not sure if this belongs here, but I'll post anyway.

If the mods move it, so be it.

Anyway, what I mean by hardware exceptions are things like divide by zero operations, invalid opcodes, general protection faults, etc.

I know that I can mask certain hardware interrupts by setting the interrupt bit in the EFLAGS register.

But, I want to know if I can do that for processor generated / hardware generated exceptions.

Thanks.

 

[Ken g6]

"maskable"? No. Handleable? I think so. It seems to depend on your OS how you declare it.

http://stackoverflow.com/questions/...eger-division-by-zero-exception-in-c-language

 

[chrstrbrts]

"maskable"? No. Handleable? I think so. It seems to depend on your OS how you declare it.

http://stackoverflow.com/questions/...eger-division-by-zero-exception-in-c-language

I think that you can mask FPU exceptions, though.

 

[Ken g6]

Floats have NaNs. So division by zero, for instance, has a defined result. Integers don't. So there's no correct result of integer division by zero and something else has to be done.

 

[chrstrbrts]

Floats have NaNs. So division by zero, for instance, has a defined result. Integers don't. So there's no correct result of integer division by zero and something else has to be done.

That makes sense.

If I remember correctly, the control register for the FPU has 6 bits, the lowest 6 bits I think, that are mask bits for the 6 types of exceptions the FPU generates.

I guess the FPU has types like NAN and QNAN to deal with unexpected outcomes, so exceptions don't need to be raised.