Discussion Apple Silicon SoC thread

[Eug]

M1
5 nm
Unified memory architecture - LP-DDR4
16 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 12 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache
(Apple claims the 4 high-effiency cores alone perform like a dual-core Intel MacBook Air)

8-core iGPU (but there is a 7-core variant, likely with one inactive core)
128 execution units
Up to 24576 concurrent threads
2.6 Teraflops
82 Gigatexels/s
41 gigapixels/s

16-core neural engine
Secure Enclave
USB 4

Products:
$999 ($899 edu) 13" MacBook Air (fanless) - 18 hour video playback battery life
$699 Mac mini (with fan)
$1299 ($1199 edu) 13" MacBook Pro (with fan) - 20 hour video playback battery life

Memory options 8 GB and 16 GB. No 32 GB option (unless you go Intel).

It should be noted that the M1 chip in these three Macs is the same (aside from GPU core number). Basically, Apple is taking the same approach which these chips as they do the iPhones and iPads. Just one SKU (excluding the X variants), which is the same across all iDevices (aside from maybe slight clock speed differences occasionally).

EDIT:



M1 Pro 8-core CPU (6+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 16-core GPU
M1 Max 10-core CPU (8+2), 24-core GPU
M1 Max 10-core CPU (8+2), 32-core GPU

M1 Pro and M1 Max discussion here:

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M1 Ultra discussion here:

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M2 discussion here:

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Second Generation 5 nm
Unified memory architecture - LPDDR5, up to 24 GB and 100 GB/s
20 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 16 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache

10-core iGPU (but there is an 8-core variant)
3.6 Teraflops

16-core neural engine
Secure Enclave
USB 4

Hardware acceleration for 8K h.264, h.264, ProRes

M3 Family discussion here:

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M4 Family discussion here:

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M5 Family discussion here:

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[jdubs03]

Is Apple using this naming scheme though? I didn't see it in their chip descriptions.

And using the P designation gets confusing because P is their middle core now.

1. Nope. They just use “performance”.
2. Yep. They face palmed the marketing on that.

 

[mavere]

Does the M5 Pro/Max adopting a big-medium setup increase the likelihood of them adopting SVE2 in near future? I assume SVE2 has implementation complexity that makes little sense for efficiency cores, but the tradeoffs are a lot different on bigger cores.

 

[johnsonwax]

Is it possible it's related to iOS 26? That wasn't a factor a year ago.

I think it's fair to say that Apple really screwed the pooch on the 26 OSs, not just on the UI issues, but they seem broadly slower on older hardware. I don't know if that's the AI additions or something else, but Apple had been pretty good about maintaining performance on older hardware through the last 5 years, but 26 seems to be a step in the wrong direction there.

 

[gdansk]

I think it's fair to say that Apple really shit the bed on the 26 OSs, not just on the UI issues, but they seem broadly slower on older hardware. I don't know if that's the AI additions or something else, but Apple had been pretty good about maintaining performance on older hardware through the last 5 years, but 26 seems to be a step in the wrong direction there.

I try not to complain about it too much, hopefully they get the message from the telemetry of me reverting to Mac OS "25". Never felt the need to do that before, I usually wait for the .1 releases and usually they're usable by then.

 

[Eug]

I don't think anyone has posted this yet. Forgive me if I'm mistaken.

Testing Apple's 2026 16-inch MacBook Pro, M5 Max, and its new "performance" cores

M5 Pro Max's "performance" CPU cores definitely aren't just rebranded E-cores.

arstechnica.com

Is Apple using this naming scheme though? I didn't see it in their chip descriptions.

Powermetrics terminology:

Super core cluster - "P-cluster"
Efficiency core cluster - "E-cluster"
Performance core cluster - "M0 cluster" and "M1 cluster"

The naming scheme is a clusterf...

 

[MerryCherry]

Is Apple using this naming scheme though? I didn't see it in their chip descriptions.

And using the P designation gets confusing because P is their middle core now.

Yeah that's what the engineers seem to be calling it - P/M/E.

(Referencing your post above).

 

[techjunkie123]

Sorry if I missed this, but how many chiplets do the M5 Pro and Max have?

 

[Nothingness]

MBP 15 vs 18 cores: https://browser.geekbench.com/v6/cpu/compare/17020813?baseline=17021005

It clearly shows which subtests have scaling limitations (nothing new, but at least the platform is fixed which makes the comparison more solid).

 

[name99]

Sorry if I missed this, but how many chiplets do the M5 Pro and Max have?

The internet seems very confident that *both* have *two* chiplets, a single CPU chiplet and a single graphics chiplet.

Unclear is if a single Max-sized graphics chiplet is manufactured which is then diced into two and each half used as a Pro chiplet.
This would require Fusion IO on both sides of the chiplet, but that seems necessary anyway for the upcoming Ultra.

Other questions not yet quite resolved include
- are the 12 M cores a single cluster or 2 clusters of 6 (or something stranger that we have not seen before, like an 8 cluster and a 4 cluster).
- the individual performance (ie something like SPEC) of a single M core.
- the area of a single M core

My bets would be
- single Max-sized graphics chiplet is manufactured, and split for pro
- two 6-sized M-clusters
- M core is 70% single threaded performance of a P, at 50% of the area. (Generically a good rule of thumb is that single-threaded performance goes up as sqrt(area) or if you prefer sqrt(num transistors).

 

[adroc_thurston]

Unclear is if a single Max-sized graphics chiplet is manufactured which is then diced into two and each half used as a Pro chiplet.

that's not how any of that works

 

[Eug]

There is an M0 and M1 cluster in the naming scheme.

 

[The Hardcard]

There is an M0 and M1 cluster in the naming scheme.

I’m surprised the board hasn’t been camera captured yet. Max Tech often dismantles them blind the first day, sometimes even before they boot it up. I always thought that was a risky thing to do before you make sure it wasn’t defective upon shipment.

 

[Doug S]

Not me this time, but seeing the Apple situation, I tought that 2P4E has reached the limit, so expecting 2P6E in a future, just like the SD8 Elite.

How has it reached the limit, when Apple added nearly 30% more performance to the 4 E cores at no cost to power in the last iteration alone?

For phone use I just don't buy that peak MT matters. There are almost no use cases where you will max out all cores and still need/want more in a phone.

Some people seem to be arguing that with the Neo using iPhone SoCs they will want to beef them up, but I don't see it. No matter how successful the Neo is it will be a single digit percentage of yearly iPhone unit sales and an even smaller single digit percentage of iPhone revenue and profit, so Apple will still design iPhone SoCs for the iPhone's needs not the Neo's.

Heck they didn't even give it improved USB to allow the Neo to have two full speed USB-C ports, something that would add almost nothing to the cost, so they aren't likely to add extra cores for the Neo's sake, not even petite little E cores. Because the phone simply doesn't have a need for more cores unless you care about pointless MT benchmark comparisons.

 

[mvprod123]

https://twitter.com/x/status/2032233047878451624

 

[gdansk]

https://twitter.com/x/status/2032233047878451624

Not bad for the Pro chip at all. I should have waited one more year to upgrade my M1 Pro but the M4 Pro was easy enough to justify after flipping the M1 Pro.
Does anyone have a 285K to run in "Eco" mode for comparison? Might be interesting. My 9950X3D scores about ~7000 in "Eco" mode (88W PPT).