I can almost guarantee you that there will not be an additional I/O chip.
After studying the die shot, and noting the complete lack of I/O on the bottom edge, I'm thinking that there's still more to this floor plan that we haven't seen yet. In other words, M1 Max is itself a chop, and Jade 2C and 4C will use a slightly longer version. Apple should be able to comfortably fit three PCIe Gen5 x16 interfaces for CXL interconnect links along the bottom edge of the die. Since Apple stuck with a conventional organic substrate and (slightly crazy) LPDDR memory, there is no issue with scaling up the package to accommodate 2 SoC dies and 8 memory packages, or even 4 SoC dies and 16 memory packages.
I'm now far less convinced that any additional DDR controllers will be forthcoming though. For a high-end iMac, the 2C maxing out at 128GB of LPDDR5 is probably fine, and depending on the design, they might even be able to jam the 4C in there. On the other hand, a Mac Pro with the 4C would max out at 256GB, which is a lot less than the current Intel Mac Pro. Perhaps this will go in the rumored smaller Mac Pro, which can be smaller because it sheds the DIMM slots and most of its PCIe slots. And maybe the big Mac Pro gets an Icelake refresh to keep that market segment satisfied for a couple years until Apple does their next round of pro chips. I guess we'll know in another 8 months.
One other thing to note about this strategy is that although there will be reduced bandwidth / increased latency between dies, Apple probably won't have to reduce clock speeds compared to the M1 Max at all. TDP will be around 340W, but whatever, that's still less than a single GA102 in an NVIDIA RTX 3090.