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Discussion Apple Silicon SoC thread

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Eug

Eug

Lifer
M1
5 nm
Unified memory architecture - LP-DDR4
16 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 12 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache
(Apple claims the 4 high-effiency cores alone perform like a dual-core Intel MacBook Air)

8-core iGPU (but there is a 7-core variant, likely with one inactive core)
128 execution units
Up to 24576 concurrent threads
2.6 Teraflops
82 Gigatexels/s
41 gigapixels/s

16-core neural engine
Secure Enclave
USB 4

Products:
$999 ($899 edu) 13" MacBook Air (fanless) - 18 hour video playback battery life
$699 Mac mini (with fan)
$1299 ($1199 edu) 13" MacBook Pro (with fan) - 20 hour video playback battery life

Memory options 8 GB and 16 GB. No 32 GB option (unless you go Intel).

It should be noted that the M1 chip in these three Macs is the same (aside from GPU core number). Basically, Apple is taking the same approach which these chips as they do the iPhones and iPads. Just one SKU (excluding the X variants), which is the same across all iDevices (aside from maybe slight clock speed differences occasionally).

EDIT:

Screen-Shot-2021-10-18-at-1.20.47-PM.jpg

M1 Pro 8-core CPU (6+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 16-core GPU
M1 Max 10-core CPU (8+2), 24-core GPU
M1 Max 10-core CPU (8+2), 32-core GPU

M1 Pro and M1 Max discussion here:

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M1 Ultra discussion here:

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M2 discussion here:

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Second Generation 5 nm
Unified memory architecture - LPDDR5, up to 24 GB and 100 GB/s
20 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 16 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache

10-core iGPU (but there is an 8-core variant)
3.6 Teraflops

16-core neural engine
Secure Enclave
USB 4

Hardware acceleration for 8K h.264, h.264, ProRes

M3 Family discussion here:

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M4 Family discussion here:

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M5 Family discussion here:

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mvprod123 said:
https://twitter.com/x/status/2032583630665691240

Click to expand...
If that chart is accurate, that is a strong indicator that the new core will replace the efficiency cores throughout the lineup. The only question is area. But I think there will be still just two cores.

That core would transform the watch capabilities and every other product up to the base M series. The phones (and Neo) will probably stay 2 + 4 and still get a significant multicore boost.
 
The Hardcard said:
If that chart is accurate, that is a strong indicator that the new core will replace the efficiency cores throughout the lineup. The only question is area. But I think there will be still just two cores.

That core would transform the watch capabilities and every other product up to the base M series. The phones (and Neo) will probably stay 2 + 4 and still get a significant multicore boost.
Click to expand...
Count me as surprised if the A20 Pro isn’t 2S+4E.
That config will still probably put out a near 12,000 GB6 nT score. Going with Ps/Ms instead of Es seems like overkill for a phone CPU.
 
jdubs03 said:
Count me as surprised if the A20 Pro isn’t 2S+4E.
That config will still probably put out a near 12,000 GB6 nT score. Going with Ps/Ms instead of Es seems like overkill for a phone CPU.
Click to expand...
Mmm... what I am thinking is that going 2P + 6E would help apple to go to use it not only on Phones but also on Macs and leave the vanilla A20 with 2P + 4E to be used on more cheap editions
 
The Hardcard said:
If that chart is accurate, that is a strong indicator that the new core will replace the efficiency cores throughout the lineup. The only question is area. But I think there will be still just two cores.

That core would transform the watch capabilities and every other product up to the base M series. The phones (and Neo) will probably stay 2 + 4 and still get a significant multicore boost.
Click to expand...
The chart appears to be the power draw of the CPU cores only, not shared cache and fabric. A big part of the power savings with the e-cores is more efficient uncore.
 
DZero said:
Mmm... what I am thinking is that going 2P + 6E would help apple to go to use it not only on Phones but also on Macs and leave the vanilla A20 with 2P + 4E to be used on more cheap editions
Click to expand...
Hopefully they’ll do something new like an A20 Max.. for the Fold and/or Neo 2. That would bridge the gap between the base and pro A20 with the base M6.

I give this a low chance of happening; but it’s doable.
 
The Hardcard said:
If that chart is accurate, that is a strong indicator that the new core will replace the efficiency cores throughout the lineup. The only question is area. But I think there will be still just two cores.

That core would transform the watch capabilities and every other product up to the base M series. The phones (and Neo) will probably stay 2 + 4 and still get a significant multicore boost.
Click to expand...

That chart doesn't tell you chip area differences between M and E. So yeah if those curves are correct then you can get slightly better than E core performance at E core's power and have all this additional legroom, so from a power and performance perspective the M core would be a clean kill fo the E core.

But if the M core is 3x the area of an E core then those will still have a role to play, especially on stuff like the watch that don't have the power budget for M cores to go beyond E core performance levels.
 
The Hardcard said:
If that chart is accurate, that is a strong indicator that the new core will replace the efficiency cores throughout the lineup. The only question is area. But I think there will be still just two cores.

That core would transform the watch capabilities and every other product up to the base M series. The phones (and Neo) will probably stay 2 + 4 and still get a significant multicore boost.
Click to expand...

Nah. Honestly feels a little bit strange.
What about getting rid of supercores in phone chips and just use the perf ones ?
I am sure a 15W core feels quite uncomfortable in a phone under load.
Or instead of 2S use one S and one P.

Or finaly make a device with just the E cores. Shall be plenty powerfull for all.
 
mvprod123 said:
This patent has revealed a lot of information about Apple PCC. https://patentscope.wipo.int/search/en/detail.jsf?docId=US469223044&_cid=P22-MMMP4H-82720-1

View attachment 139902
View attachment 139903

View attachment 139904
Click to expand...
That's what's being made today (we saw what looks very much like this in a recent PR video, I think made with The WSJ) of Apple's factory in Texas.

But the (possible) future looks much more exciting:

US20250094093A1 - Optics-Based Distributed Unified Memory System - Google Patents

Techniques are disclosed relating to computing systems that use silicon photonics. In some embodiments, a computing system includes a plurality of compute die packages that include processors configured to execute program instructions that operate on data stored in a distributed memory...
patents.google.com
 
The Hardcard said:
If that chart is accurate, that is a strong indicator that the new core will replace the efficiency cores throughout the lineup. The only question is area. But I think there will be still just two cores.

That core would transform the watch capabilities and every other product up to the base M series. The phones (and Neo) will probably stay 2 + 4 and still get a significant multicore boost.
Click to expand...
Maybe.
But another way to drive things is using Intel's LE core as a model...

Obviously not literally, but with the idea that while M cores apparently scale well from low energy to fine levels of throughput (at low area and power) even at their lowest clocking they may be overkill for many phone and watch situations (for example the background work as your phone occasionally checks the network and responds to notifications and email).
What if going forward we give every SoC two truly tiny cores, maybe 2-wide in-order, min clock of maybe .1 GHz and max clock of whatever the process supports? With no need to even care about performance (that's M's job) these cores can be truly, ridiculously low power and low area.

Both phone and watch would probably benefit a lot from this, having two or four M cores for work when the user is waiting, while handling all the non-user-waiting stuff slowly but on almost zero power.
 
name99 said:
Obviously not literally, but with the idea that while M cores apparently scale well from low energy to fine levels of throughput (at low area and power) even at their lowest clocking they may be overkill for many phone and watch situations (for example the background work as your phone occasionally checks the network and responds to notifications and email).
What if going forward we give every SoC two truly tiny cores, maybe 2-wide in-order, min clock of maybe .1 GHz and max clock of whatever the process supports? With no need to even care about performance (that's M's job) these cores can be truly, ridiculously low power and low area.

Both phone and watch would probably benefit a lot from this, having two or four M cores for work when the user is waiting, while handling all the non-user-waiting stuff slowly but on almost zero power.
Click to expand...

This is what Android World did for a long time with A7's, A53's, and A55's - even down to the point of being 2-wide in-order.
 
GC2:CS said:
Nah. Honestly feels a little bit strange.
What about getting rid of supercores in phone chips and just use the perf ones ?
I am sure a 15W core feels quite uncomfortable in a phone under load.
Or instead of 2S use one S and one P.

Or finaly make a device with just the E cores. Shall be plenty powerfull for all.
Click to expand...

Their P cores are nowhere near 15 watts. I can run my 16 Pro Max flat out and it gets a bit warm. Most phones get a lot warmer or even downright hot, especially ones using Qualcomm's latest that are pushing the clock rates WAY more than Apple.

Why are people questioning Apple's strategy when they sell a quarter billion iPhones a year, and it is easily the most profitable product in the history of mankind?

But no, random forum posters think they know better and Apple should copy all the failed strategies of past Android OEMs.
 
poke01 said:
Rough M5 P/M/E diagrams.

View attachment 139996

View attachment 139997
View attachment 139998

SPEC results:
View attachment 139999

since the M core builds on E core its pretty efficient too at 2.5watts.
https://tieba.baidu.com/p/10552266923?fr=personpage
https://tieba.baidu.com/p/10551185246?fr=personpage
Click to expand...
Nice find!

That FP and INT score for the S/P core is ridiculous. Looking at Geekerwan’s M5 info this is quite a bit higher. Do we know the chosen variables and the compiler?
1773559844953.jpeg
 
jdubs03 said:
Nice find!

That FP and INT score for the S/P core is ridiculous. Looking at Geekerwan’s M5 info this is quite a bit higher. Do we know the chosen variables and the compiler?
View attachment 140000
Click to expand...
I'll never get over the iPhone processor outpacing a desktop x86 by that much. I remember well the A7 launch, after everyone was screaming that Apple was incapable of designing their own cores, it became clear they could so they screamed that there was no point to a 64bit SOC in a phone. If only they knew where that would lead.
 
Doug S said:
Why are people questioning Apple's strategy when they sell a quarter billion iPhones a year, and it is easily the most profitable product in the history of mankind?

But no, random forum posters think they know better and Apple should copy all the failed strategies of past Android OEMs.
Click to expand...
It's only fair that people try to second guess vendors on this forum, that's what we do as part of the hobby. The part that we need to keep in mind is that the second-guessing is more about our learning process than giving lessons to some of the best professionals in the industry.

Even if we don't respect the people, we can at least respect the data, or the lack of it: we often get to play with telemetry that tells just part of the story (can be truncated, can be less accurate at either end of the spectrum). It's the best we can get as outsiders and we should use it, but it still paints a relatively blurry picture.
 
poke01 said:
Rough M5 P/M/E diagrams.

View attachment 139996

View attachment 139997
View attachment 139998

SPEC results:
View attachment 139999

since the M core builds on E core its pretty efficient too at 2.5watts.
https://tieba.baidu.com/p/10552266923?fr=personpage
https://tieba.baidu.com/p/10551185246?fr=personpage
Click to expand...

So, if accurate - vs the e-core, they went from 2LS to 2L+2S, kept the branch predictors and caches mostly in place, went for wider decode, removed a simple ALU, and bumped some structure sizes?

Perf/clock is pretty similar between the M5 e-core and the m-core - if these diagrams and SPEC runs are accurate, are we sure the M-core isn't just a new-gen e-core microarchitecture with a more aggressive physical design and a higher target clock?
 
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