Discussion Apple Silicon SoC thread

[senttoschool]

Apple uses the SLC more for power savings than performance improvement.

Yep. M1/M2 runs at a higher frequency to make up for the loss of cache.

Also, I don't think it's too bizarre that the cache stayed the same from M1 to M2. They didn't really design brand-new cores and they used the N5 process so there isn't much more room for more cache.

 

[FlameTail]

Oh yeah, one reason that explains the doubling of SLC from A14 (16MB) to A15 (32 MB) is memory bandwidth limitations. A15 skipped LPDDR5 and continued to use LPDDR4X, and considering the dramatic GPU performance jump from A14 -> A15, they certainly hit a bandwidth limit.

The fact that the A16 regressed to a 24 MB SLC from the A15 seems to prove this point. A16 added LPDDR5.

 

[Doug S]

Oh yeah, one reason that explains the doubling of SLC from A14 (16MB) to A15 (32 MB) is memory bandwidth limitations. A15 skipped LPDDR5 and continued to use LPDDR4X, and considering the dramatic GPU performance jump from A14 -> A15, they certainly hit a bandwidth limit.

The fact that the A16 regressed to a 24 MB SLC from the A15 seems to prove this point. A16 added LPDDR5.

Exactly.

I imagine Apple runs simulations based on model iPhone and Mac workloads to determine the sweet spot for SLC size. So if 32 MB was the sweet spot based on LPDDR4X's power/performance profile, then with LPDDR5 adding bandwidth and reducing power 24 MB was sufficient.

 

[MadRat]

Might not involve simulations at all. Maybe LPDDR4X used 4x8MB caching whereas LPDDR5 perhaps may use 3x8MB to reduce chip realestate for equivalent bandwidth and lower latency access times. The fourth cache may even still be there, but dormant until the next reiteration. Why play all your cards immediately?

 

[Eug]

A12Z Mac mini DTK benchmarks and teardown
- Came with macOS 10.16 (which doesn't officially exist)
- Does not support Thunderbolt
- Fan speed never changes
- Has 3 coin batteries on the mobo

Cinebench R23
A12Z - 4353 (I'm assuming this is native, not Rosetta 2)
M1 - 7833 (Native, from AnandTech review)



Blender BMW (no Metal)
A12Z Mac mini (8-core GPU) - 8:59
M1 iMac (7-core GPU) - 5:38

Final Cut Pro render
A12Z - 17'44"
M1 - 13'37"
i5-8500B - 64'22"

Motherboards: Core i5-8500B Mac mini | A12Z Mac mini | M1 Mac mini



I wonder if Apple is going to hassle him over this. FWIW, he didn't sign any developer NDA. He bought the thing off eBay.

 

[senttoschool]

Why would anyone that spends $10,000+ on a workstation for conceivably projects worth 10x-1000x the value of the workstation, want their data to touch Apple's cloud? That is ludicrous. Apple would be in position to spy on their information and possibly perform espionage. Anyone that believes Apple would not, I have a line of premium bridges to sell you.

I didn't know Apple was in the business of stealing in-progress production projects and selling them on the black market.

 

[Doug S]

I didn't know Apple was in the business of stealing in-progress production projects and selling them on the black market.

If he hate Apples enough, I guess he will believe any crazy thing. Sounds like the Qanon of the tech world lol

 

[senttoschool]

If he hate Apples enough, I guess he will believe any crazy thing. Sounds like the Qanon of the tech world lol

If Apple wanted to, they can easily do this. They can simply install some spyware on macOS and send everything to Apple. Heck, iCloud data is not encrypted. So they can steal their user's work now.

I've never read anything about Apple selling stolen user projects though. So maybe the project @MadRat is working on could be the first to be stolen and sold by Apple.

 

[uzzi38]

https://twitter.com/i/web/status/1608433753201971201

https://twitter.com/i/web/status/1608434897193951232

So can we finally agree that the base N3 is a dud?

#WaitForN3EOrN4P

 

[Doug S]

TSMC has said they could pull in N3E. Given how little interest there is on the base N3 it makes sense for them to push it forward as much as possible.

Since it uses more relaxed design rules (primarily to avoid multipatterning in EUV) and uses N5's SRAM cells I don't see why it can't enter mass production in Q2 next year if that's what Apple wants. There's absolutely no reason for TSMC to need a year or want to wait a year for N3E to enter mass production unless they don't have any major customers with N3E designs taped out yet.

 

[jpiniero]

There's absolutely no reason for TSMC to need a year or want to wait a year for N3E to enter mass production unless they don't have any major customers with N3E designs taped out yet.

Probally still needs some work to be done.

 

[smalM]

TSMC has said they could pull in N3E. Given how little interest there is on the base N3 it makes sense for them to push it forward as much as possible.

Since it uses more relaxed design rules (primarily to avoid multipatterning in EUV) and uses N5's SRAM cells I don't see why it can't enter mass production in Q2 next year

CC Wei said N3E might be pushed forward one or two or three months. (Q3 Earnings Conference Transcript - Page 20)

 

[Doug S]

CC Wei said N3E might be pushed forward one or two months.

The only comments I could find attributed directly to him were in April, "And pull-in, yes, we are considering that. So far, I still did not have a very solid data to share with you that how many months we can pull in. But yes, it is in our plan."

The March report from Morgan Stanley was that it could be pulled forward by a quarter to begin mass production in Q2 2023. That was back when N3 was still supposed to start mass production in September. We now know N3 mass production happened three months later than that, but the open question is: was that due to issues that will also delay N3E or due to issues specific to N3? We don't know that answer. If N3's delay from September to December was due to issues that were addressed by N3E, those three months will not push back N3E's debut but instead compress the timeline between N3 and N3E even further.

Also consider the yield graph that was leaked back in August, showing 80% yields already for N3E on "mobile and HPC test chips". I don't know what yield TSMC requires before considering a process risk production or mass production worthy, but N5 entered risk production with yields below 80%. TSMC has always introduced new nodes that improved upon previous nodes in density, power or performance - often all three. So it makes sense you'd need and want a lengthy risk production cycle to insure that those improvements can be delivered consistently in volume, with good yields.

This is the first time they've introduced a new node that has worse density, worse power, and worse performance. Maybe I'm crazy but it seems to me that risk production ought to be a lot quicker when you are rolling out a node that's less aggressive than what came before, instead of like in every other case more aggressive. Additionally, I would think that customers would be more likely to consider buying some risk production wafers to use in their products if they get a bit of a discount to reflect the slightly reduced yields.

 

[FlameTail]

There is no way Apple is going to pass over 3nm and keep using 4nm for the A17 Bionic. That would mean the Android mobile SoCs coming at the end of the year that would get the 3nm node would have a superior advantage, which i am sure Apple doesn't want to happen.

 

[LightningZ71]

With the above comment about N3E using the N5 SRAM cells with some relaxing of the design rules for the rest of the chip, I think that that speaks to two specific problems: the metrics for N3 were too tight for decent yields and they couldn't get their N3 SRAM design rules to provide sufficient power/performance/density at reasonable yields. They are soldiering on ahead with N3, but taking a yield hit in the process, leaving only customers that can afford very high functional die costs. To recover some of the investment, they introduced N3E to provide for a high enough yield that customers would want to pay enough per wafer to cover their R&D and production costs. Being able to use different fin arrangement on the same die by zones may be the one thing that actually saves N3 for TSMC. I think that, without that, N3 would have had a lot harder time gaining traction.

 

[jpiniero]

With the above comment about N3E using the N5 SRAM cells with some relaxing of the design rules for the rest of the chip, I think that that speaks to two specific problems: the metrics for N3 were too tight for decent yields and they couldn't get their N3 SRAM design rules to provide sufficient power/performance/density at reasonable yields. They are soldiering on ahead with N3, but taking a yield hit in the process, leaving only customers that can afford very high functional die costs. To recover some of the investment, they introduced N3E to provide for a high enough yield that customers would want to pay enough per wafer to cover their R&D and production costs. Being able to use different fin arrangement on the same die by zones may be the one thing that actually saves N3 for TSMC. I think that, without that, N3 would have had a lot harder time gaining traction.

TSMC says yields of N3 are good. It's simply that N4P is comparable in quality and cheaper/transistor so there's not much point unless you need the smaller size. N3E improves the quality to make it worthwhile despite the reduction in density compared to N3.

 

[Ajay]

TSMC says yields of N3 are good. It's simply that N4P is comparable in quality and cheaper/transistor so there's not much point unless you need the smaller size. N3E improves the quality to make it worthwhile despite the reduction in density compared to N3.

Performance (N3E) will likely be better than N3B, for those who need it. It'll also be a bit cheaper, I think, with fewer masks. The big question for me, is does Apple buy out N3E risk production to get A17 on N3E (maybe just for iPhone Pro models). Supposedly, Apple is using N3B - so, IDK what's really going on.

 

[Doug S]

Performance (N3E) will likely be better than N3B, for those who need it. It'll also be a bit cheaper, I think, with fewer masks. The big question for me, is does Apple buy out N3E risk production to get A17 on N3E (maybe just for iPhone Pro models). Supposedly, Apple is using N3B - so, IDK what's really going on.

The only rumors I've seen for Apple using N3/N3B is for M2 Pro/Max. And we can't even be 100% sure of that, I wouldn't be shocked to see them drop M2 Pro/Max entirely when September mass production became December mass production if N3E was getting pulled in sufficiently (using their M3 Pro/Max designs, which will have taped out for N3E) With December mass production, unless they are using N3 risk wafers the earliest they could ship systems would be April. If N3E mass production was able to be pushed into Q2 like Morgan Stanley claimed, that's only a 4-5 month delay...

N3E will definitely be cheaper, but performance of "golden chips" should be better on N3B since it is the more aggressive process. But for the "mean chip" or "the mean + two standard deviations" (i.e. the desired yield bell curve) then I'd agree with you. N3E performance should be better, because the "bad but working" N3B chips may not be all that good.

 

[Eug]

AMD announced Ryzen 7040 series laptop chips at CES.
N4, 25 billion transistors.

Compared against M1 Pro and M2.



30% faster than Apple M1 Pro in Blender render, and 45% faster than Intel Core i7-1280P. Not sure how Blender test was set up.



30 hours video playback on battery.

 

[richardskrad]

AMD trying to be slick, lol. The only relevant benchmark for comparison x86 and ARM is Geekbench - not Cinebench, Blender, etc.

 

[Mopetar]

Apple getting a free mention in a CES keynote is pretty funny.

 

[richardskrad]

https://twitter.com/i/web/status/1610847756394065921

 

[Hitman928]

https://twitter.com/i/web/status/1610847756394065921

That guy doesn't know what he is talking about, as others in that twitter thread point out.

 

[Ajay]

That guy doesn't know what he is talking about, as others in that twitter thread point out.

Well, yeah, they point out that the audio techs are likely contracted. Still funny tho.

 

[DrMrLordX]

AMD trying to be slick, lol. The only relevant benchmark for comparison x86 and ARM is Geekbench - not Cinebench, Blender, etc.

They're showing off Phoenix's fp performance in memory/cache-independent benchmarks. You have a problem with that?