Discussion Apple Silicon SoC thread

[Eug]

M1
5 nm
Unified memory architecture - LP-DDR4
16 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 12 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache
(Apple claims the 4 high-effiency cores alone perform like a dual-core Intel MacBook Air)

8-core iGPU (but there is a 7-core variant, likely with one inactive core)
128 execution units
Up to 24576 concurrent threads
2.6 Teraflops
82 Gigatexels/s
41 gigapixels/s

16-core neural engine
Secure Enclave
USB 4

Products:
$999 ($899 edu) 13" MacBook Air (fanless) - 18 hour video playback battery life
$699 Mac mini (with fan)
$1299 ($1199 edu) 13" MacBook Pro (with fan) - 20 hour video playback battery life

Memory options 8 GB and 16 GB. No 32 GB option (unless you go Intel).

It should be noted that the M1 chip in these three Macs is the same (aside from GPU core number). Basically, Apple is taking the same approach which these chips as they do the iPhones and iPads. Just one SKU (excluding the X variants), which is the same across all iDevices (aside from maybe slight clock speed differences occasionally).

EDIT:



M1 Pro 8-core CPU (6+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 14-core GPU
M1 Pro 10-core CPU (8+2), 16-core GPU
M1 Max 10-core CPU (8+2), 24-core GPU
M1 Max 10-core CPU (8+2), 32-core GPU

M1 Pro and M1 Max discussion here:

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M1 Ultra discussion here:

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M2 discussion here:

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Second Generation 5 nm
Unified memory architecture - LPDDR5, up to 24 GB and 100 GB/s
20 billion transistors

8-core CPU

4 high-performance cores
192 KB instruction cache
128 KB data cache
Shared 16 MB L2 cache

4 high-efficiency cores
128 KB instruction cache
64 KB data cache
Shared 4 MB L2 cache

10-core iGPU (but there is an 8-core variant)
3.6 Teraflops

16-core neural engine
Secure Enclave
USB 4

Hardware acceleration for 8K h.264, h.264, ProRes

M3 Family discussion here:

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[jpiniero]

since all M1 Ultras are sold with their full complement of CPU and GPU cores.

That is not true. The base model has the GPU cores cut. It's an extra grand for the full version.

 

[Eug]

That is not true. The base model has the GPU cores cut. It's an extra grand for the full version.

Yep. M1, M1 Pro, M1 Max, and M1 Ultra all have binned variants.

M1 Pro is the only one with different bins of CPU cores though.
The rest are binned by GPU core counts.

 

[ashFTW]

Great find on that article with the patent links! Where did you find the picture you linked with the interposer in the center? The article references three patents but I don't see that anywhere.

I think I screenshot it from the Max Tech video I linked above.

Apple patent US20220013504A1
Aople patent US20210217702A1
TSMC patent US20210305146A1

Thanks for the links to the patents.

If you look at this picture, it implies the possibility that four dies could be carved out and all connected together. If 2.5 TB/sec is enough for four, maybe that's how they'll do it, though that's less efficient than my sandwich in terms of wire delay.

Yes, absolutely agree. The sandwich idea is more efficient, but it maybe harder to yield. But I would love to see it implemented that way.

 

[repoman27]

Apple is not stitching adjacent dies for M1 Ultra. They're almost certainly using TSMC CoWoS-L or a similar variation of that technology proprietary to Apple. The relevant Apple patent would be US20210159180A1 as reported by ComputerWorld. TSMC's advanced packaging roadmap has also been covered previously by Anandtech. During the Apple presentation, Johny Srouji specifically said that they were connecting two M1 Max dies using a silicon interposer, and the accompanying graphics certainly appear to show two singulated M1 Max dies coming together and being joined by an interposer chiplet sitting below them. I don't think there's any reason to believe they are misrepresenting this.

I'd also pay attention to what Hector Martin is saying, because he's got a very good handle on M1 hardware. There probably is no chip forthcoming that uses four M1 Max dies, and no possibility of a "multi-socket" M1 Ultra. Seeing as the M1 Ultra isn't socketed, it would simply be a multi-processor configuration, which of course is a tried and true topology. However, the highest bandwidth interface the M1 Ultra has available for chip-to-chip communication would be PCI Express Gen4 x4—at just 16 GB/s aggregate bandwidth before you even account for encoding and protocol overhead. So that idea is a non-starter.

The die-to-die interface that the M1 Ultra uses does seem like it could provide sufficient bandwidth for four dies though. The LPDDR5-6400 memory interfaces on the M1 Max can theoretically provide peak bandwidth of 409.6 GB/s. Double that for a bidirectional link between two dies and you're at 819.2 GB/s. Triple that for a 4-die all-way link and you get 2.4576 TB/s. Apple claims that UltraFusion can provide 2.5 TB/s of interprocessor bandwidth. 🤔

This is certainly enough to make one ponder how Apple might package four M1 Max dies along with memory for a Mac Pro system, and I'm right there along with everyone else going down that rabbit-hole. But in the end, I don't think it's going to happen with this generation of chips.

 

[jpiniero]

https://twitter.com/x/status/1503033974473760768

Ooh, spicy rumor that the base 2022 iPhone will have the same A15 processor as the current model. I don't necessarily think it's a supply thing but it's a combination of N4 wafers being more expensive and Apple trying to get higher ASPs by pushing the Pro model harder.

 

[Eug]

https://twitter.com/x/status/1503033974473760768

Ooh, spicy rumor that the base 2022 iPhone will have the same A15 processor as the current model. I don't necessarily think it's a supply thing but it's a combination of N4 wafers being more expensive and Apple trying to get higher ASPs by pushing the Pro model harder.

I was a little bit surprised that the low cost SE got A15. I have A14 in my iPhone 12 Pro Max, and it's blistering fast. In fact, my iPhone is the fastest "computer" in my entire house!

I was wondering if maybe they'd go for A14 for iPhone SE, but they went with the latest and greatest A15.

 

[repoman27]

So given that the M1 Max die is roughly square and 432 mm^2, that bottom edge is about 20 mm, in which over 10,000 I/Os are presented. That's one every 2 um along the edge...

The 432 mm² was based on the image provided by Apple showing the M1 family lineup, assuming 1:1 scale, and not knowing that the bottom of the M1 Max had been cropped off.

My best estimate, based on the M1 being 119 mm², using the highest resolution images provided by Apple for each chip, and measuring the CPU core block to determine scale, comes in slightly under Andrei's:

M1 Max (including multi-die interconnect) = 18.26 mm x 21.36 mm = 390 mm²
M1 Ultra (two dies plus shared interposer) = 18.26 mm x 42.72 mm = 780 mm²

Either way, that's a still a lot of TSMC N5 silicon. There's no way Apple could have done 2-up with a single set of masks and a reticle limit of 26 mm x 33 mm.

I also tried to establish solid lower and upper bounds for the cost of a fully functional M1 Ultra based on the price of the Mac Studio. Apple's full retail price on that 780 mm² behemoth is somewhere in the $2900 to $3500 range (not including DRAM), which is pretty decent when you compare it to similarly sized chips from Intel.

 

[The Hardcard]

Apple is not stitching adjacent dies for M1 Ultra. They're almost certainly using TSMC CoWoS-L or a similar variation of that technology proprietary to Apple. The relevant Apple patent would be US20210159180A1 as reported by ComputerWorld. TSMC's advanced packaging roadmap has also been covered previously by Anandtech. During the Apple presentation, Johny Srouji specifically said that they were connecting two M1 Max dies using a silicon interposer, and the accompanying graphics certainly appear to show two singulated M1 Max dies coming together and being joined by an interposer chiplet sitting below them. I don't think there's any reason to believe they are misrepresenting this.

I'd also pay attention to what Hector Martin is saying, because he's got a very good handle on M1 hardware. There probably is no chip forthcoming that uses four M1 Max dies, and no possibility of a "multi-socket" M1 Ultra. Seeing as the M1 Ultra isn't socketed, it would simply be a multi-processor configuration, which of course is a tried and true topology. However, the highest bandwidth interface the M1 Ultra has available for chip-to-chip communication would be PCI Express Gen4 x4—at just 16 GB/s aggregate bandwidth before you even account for encoding and protocol overhead. So that idea is a non-starter.

The die-to-die interface that the M1 Ultra uses does seem like it could provide sufficient bandwidth for four dies though. The LPDDR5-6400 memory interfaces on the M1 Max can theoretically provide peak bandwidth of 409.6 GB/s. Double that for a bidirectional link between two dies and you're at 819.2 GB/s. Triple that for a 4-die all-way link and you get 2.4576 TB/s. Apple claims that UltraFusion can provide 2.5 TB/s of interprocessor bandwidth. 🤔

This is certainly enough to make one ponder how Apple might package four M1 Max dies along with memory for a Mac Pro system, and I'm right there along with everyone else going down that rabbit-hole. But in the end, I don't think it's going to happen with this generation of chips.

You don’t have to cut two days apart to connect them to an interposer through an interposer. I think the graphic was just a conceptualization graphic in that related to the actual physical making of an M1 ultra. Look at the image of M1 Ultra itself. It’s one piece.

I also think the M1 generation was a way to work on multiple ends of the four dies issue. Clearly, the M1 architecture doesn’t support connecting four dies, but we already see with the A15 that they are making the necessary changes to do that. There’s probably going to be everything needed for four dies to work visible within the A16. And I suspect M2 family chips to be based on A16.

I’m going to speculate that the reason non-Pro iPhone 14s won’t get the A16 is that A16/M2 family is going to be more complex and costly.

 

[Roland00Address]

I was a little bit surprised that the low cost SE got A15. I have A14 in my iPhone 12 Pro Max, and it's blistering fast. In fact, my iPhone is the fastest "computer" in my entire house!

I was wondering if maybe they'd go for A14 for iPhone SE, but they went with the latest and greatest A15.

If I were to guess the reason for the SE got the A15 is that it has a 40% faster neural engine and a new ISP. This allows the Phone to have all their phones of the same generation to get any new features that require the new ISP or faster neural engine.

 

[DrMrLordX]

Ooh, spicy rumor that the base 2022 iPhone will have the same A15 processor as the current model. I don't necessarily think it's a supply thing but it's a combination of N4 wafers being more expensive and Apple trying to get higher ASPs by pushing the Pro model harder.

There may also be a fairly limited number of iOS users that will notice or care.

 

[repoman27]

You don’t have to cut two days apart to connect them to an interposer through an interposer. I think the graphic was just a conceptualization graphic in that related to the actual physical making of an M1 ultra. Look at the image of M1 Ultra itself. It’s one piece.

We only have renders provided by Apple at this point, not photos of the actual chip.

Given the dimensions I noted earlier, you can fit 151 M1 Max dies on a single wafer. If the M1 Ultra required two adjacent dies, you could only carve 68 out of that same wafer (plus 15 bonus M1 Max dies from around the edges). Furthermore, you'd need adjacent dies free from killer defects, which would be less likely. Using the Seeds model and assuming a D0 of 0.08 defects / cm², that would give you 115 yielded M1 Max dies per wafer, from which you could build 57.5 M1 Ultras. Meanwhile you'd be lucky to get 42 yielded M1 Ultras if they had to be a single contiguous piece of silicon. That's a 27% reduction in yields at the same defect density.

Furthermore, by building a reconstituted wafer using known good dies (the CoW method), you can test first and select from thousands of dies taken from hundreds of different wafers to create matched pairs that maximize the number of M1 Ultras you can build that will meet the minimum functional, power, and performance requirements. The increase in parametric yields would be huge.

Then there's the problem of the two dies together exceeding the 26 mm x 33 mm reticle limit. The M1 Max die lacks the symmetry required for conventional stitching. To get two dies back to back like that, you'd need to run it through the stepper twice, exposing alternate positions with the mask / wafer rotated 180º. That wouldn't be trivial, considering TSMC N5 already uses multiple patterning and EUV for many layers. The risk of defects due to alignment errors would increase significantly, and cycle times would extend dramatically.

Seeing as Apple's retail pricing for the M1 Ultra is between $2900 and $3500, it really has to be built from two smaller dies.

 

[Ajay]

I’m going to speculate that the reason non-Pro iPhone 14s won’t get the A16 is that A16/M2 family is going to be more complex and costly.

I think this isn't an unreasonable prediction. In order to significant advance performance on A16/M2, with the fairly small area shrink (though, probably a bit better for Apple than the public 6% figure); these SoCs will be going up in size, and will result in fewer dice/wafer. Seems like a reasonable move given the delay in N3/N3E.

 

[The Hardcard]

We only have renders provided by Apple at this point, not photos of the actual chip.

Given the dimensions I noted earlier, you can fit 151 M1 Max dies on a single wafer. If the M1 Ultra required two adjacent dies, you could only carve 68 out of that same wafer (plus 15 bonus M1 Max dies from around the edges). Furthermore, you'd need adjacent dies free from killer defects, which would be less likely. Using the Seeds model and assuming a D0 of 0.08 defects / cm², that would give you 115 yielded M1 Max dies per wafer, from which you could build 57.5 M1 Ultras. Meanwhile you'd be lucky to get 42 yielded M1 Ultras if they had to be a single contiguous piece of silicon. That's a 27% reduction in yields at the same defect density.

Furthermore, by building a reconstituted wafer using known good dies (the CoW method), you can test first and select from thousands of dies taken from hundreds of different wafers to create matched pairs that maximize the number of M1 Ultras you can build that will meet the minimum functional, power, and performance requirements. The increase in parametric yields would be huge.

Then there's the problem of the two dies together exceeding the 26 mm x 33 mm reticle limit. The M1 Max die lacks the symmetry required for conventional stitching. To get two dies back to back like that, you'd need to run it through the stepper twice, exposing alternate positions with the mask / wafer rotated 180º. That wouldn't be trivial, considering TSMC N5 already uses multiple patterning and EUV for many layers. The risk of defects due to alignment errors would increase significantly, and cycle times would extend dramatically.

Seeing as Apple's retail pricing for the M1 Ultra is between $2900 and $3500, it really has to be built from two smaller dies.

The evidence is rapidly and consistently mounting the those are actual die shots, and the only modification was cropping the interconnect out of the M1 Max die shot.

Why would the wafer have to be turned when two M1 Maxes with interconnects facing each other can be made on one maak? The calculations that put two M1 Maxes over the reticle limit are off. They do fit.

I have no doubt that among the first orders werethose who make a business of buying Apple products so they can immediately tear the devices apart and post pics online. I’m sure they already know that clear and detailed images of M1 Ultra will go viral. Those are going to be pics of a single piece.

Unless Apple spent time, space, and money making it almost impossible to see the die without busting it up. Sadly, frustratingly, that is possible.

EDIT: I think the pricing also screams two dies on one cut. Putting together two 32-core Maxes wouldn’t cost more than connecting two 24-core chips. Yet a full-on Ultra is not double the full M1 Max price, it is five times higher $1000 vs. $200.

 

[Doug S]

Apple is not stitching adjacent dies for M1 Ultra. They're almost certainly using TSMC CoWoS-L or a similar variation of that technology proprietary to Apple. The relevant Apple patent would be US20210159180A1 as reported by ComputerWorld. TSMC's advanced packaging roadmap has also been covered previously by Anandtech. During the Apple presentation, Johny Srouji specifically said that they were connecting two M1 Max dies using a silicon interposer, and the accompanying graphics certainly appear to show two singulated M1 Max dies coming together and being joined by an interposer chiplet sitting below them. I don't think there's any reason to believe they are misrepresenting this.

I'd also pay attention to what Hector Martin is saying, because he's got a very good handle on M1 hardware. There probably is no chip forthcoming that uses four M1 Max dies, and no possibility of a "multi-socket" M1 Ultra. Seeing as the M1 Ultra isn't socketed, it would simply be a multi-processor configuration, which of course is a tried and true topology. However, the highest bandwidth interface the M1 Ultra has available for chip-to-chip communication would be PCI Express Gen4 x4—at just 16 GB/s aggregate bandwidth before you even account for encoding and protocol overhead. So that idea is a non-starter.

The die-to-die interface that the M1 Ultra uses does seem like it could provide sufficient bandwidth for four dies though. The LPDDR5-6400 memory interfaces on the M1 Max can theoretically provide peak bandwidth of 409.6 GB/s. Double that for a bidirectional link between two dies and you're at 819.2 GB/s. Triple that for a 4-die all-way link and you get 2.4576 TB/s. Apple claims that UltraFusion can provide 2.5 TB/s of interprocessor bandwidth. 🤔

This is certainly enough to make one ponder how Apple might package four M1 Max dies along with memory for a Mac Pro system, and I'm right there along with everyone else going down that rabbit-hole. But in the end, I don't think it's going to happen with this generation of chips.

I agree with your sentiment that this is very likely the end of the line for M1. The four SoC Mac Pro will be made using M2, the current speculation is just based on M1 because that's what we know about now. We have to keep in mind that if they never ship any four SoC Mac Pros based on M1, that doesn't mean they wouldn't want to provide themselves some way to build some internally to further development - even if the way they are built isn't how they plan to do the release version.

I'm not totally sold on the adjacent die thing either, but look at the patents. This is what they talk about. I'm not sure how the die stitching on the wafer actually works, Apple wouldn't be the first to do it because you have the example of Cerebras who have done it with TSMC for N7 and now N5 stitching ALL their dies together. I didn't know you could get that density of interconnect but what I don't know about advanced processes would fill an Olympic sized pool so along with the patents it has to be considered. Now maybe the die stitching is only used to the extent of being able to test two dies together to verify all the connections between them, then they are cut and separately placed on the interposer. That would explain how Srouji described it. Who knows, maybe the patent describes what will happen with M2 not what they are doing with M1...

Given the Cerebras example, the die stitching is not limited by the reticle size, otherwise they would not be able to produce a wafer full of interconnected dies. So we have to consider that the M2 might have more stitching instead of just off the bottom. If the stitches can have multiple metal layers, a 2x2 quad of M2 dies could be interconnected on two edges and a corner (with routing underneath where the corners cross) if each die was flipped 90* so all the corners met. Based on the images in the patents, it sounds like Apple is flipping half the M1 Max dies on a wafer - or at least that it is possible to do. Not sure what would be involved in the stepper flipping or rotating images as it exposes a wafer, but even if this isn't a built in capability and it adds additional steps it wouldn't impact cost THAT much considering how many steps there are. If it added 10% to the wafer cost that's a few tens of dollars which makes no difference to Apple considering the ASPs of the hardware where the Max, Ultra and "Extreme" Apple Silicon is going. Having four in a box leaves two edges for the four LPDDR stacks that surround each SoC.

 

[Doug S]

The evidence is rapidly and consistently mounting the those are actual die shots, and the only modification was cropping the interconnect out of the M1 Max die shot.

Why would the wafer have to be turned when two M1 Maxes with interconnects facing each other can be made on one maak? The calculations that put two M1 Maxes over the reticle limit are off. They do fit.

I have no doubt that among the first orders werethose who make a business of buying Apple products so they can immediately tear the devices apart and post pics online. I’m sure they already know that clear and detailed images of M1 Ultra will go viral. Those are going to be pics of a single piece.

Unless Apple spent time, space, and money making it almost impossible to see the die without busting it up. Sadly, frustratingly, that is possible.

EDIT: I think the pricing also screams two dies on one cut. Putting together two 32-core Maxes wouldn’t cost more than connecting two 24-core chips. Yet a full-on Ultra is not double the full M1 Max price, it is five times higher $1000 vs. $200.

The reticle limit isn't just about mm^2, it is about length and width. For ASML's EUV machines, the reticle is 26x33 mm. They definitely aren't exposing two M1 Max dies together, they don't fit in those dimensions. To have dies on the wafer back to back they need to flip the image in the EUV scanner. How difficult that is or how much cost it adds, we don't know. With the high NA EUV scanners coming soon the reticle shrinks to 26x16.5 mm. That's part of the reason everyone is rushing to go chiplet based, because the 500 - 700 mm^2 beasts Intel and Nvidia have sold for years will not be possible soon without some sort of chiplets or die stitching.

As for the pricing thing, Apple's actual cost has nothing to do with the $1000 higher price but on what their customers are willing to pay. Where do you think all that profit comes from?

 

[Schmide]

2.5 TBs in perspective.

pcie 4 = ~2 GBs per lane = 1250 lanes
pcie 5 = ~4 GBs per lane = 625 lanes
Infinity Fabric 3.0 = ~25 Gbs per pin, 16 pins per link 100 GB/s (50 bidirectional) = 25 Infinity Fabric 3.0 links

An instinct mi250 has 8 Infinity Fabric 3.0 links for a total of 800 GB/s (400 bidirectional)

M1 Ultra is 3.2x mi250

 

[Eug]

I agree with your sentiment that this is very likely the end of the line for M1.

Just in case you missed the posts earlier about this, Apple already said it's the end of the line for M1.

M1 Ultra is another game-changer for Apple silicon that once again will shock the PC industry. By connecting two M1 Max die with our UltraFusion packaging architecture, we’re able to scale Apple silicon to unprecedented new heights. With its powerful CPU, massive GPU, incredible Neural Engine, ProRes hardware acceleration, and huge amount of unified memory, M1 Ultra completes the M1 family as the world’s most powerful and capable chip for a personal computer.

Apple unveils M1 Ultra, the world’s most powerful chip for a personal computer

Apple today announced M1 Ultra, the next giant leap for Apple silicon and the Mac.

www.apple.com

 

[repoman27]

I didn't see these photos from the テカナリエ清水 @techanalye1 Twitter account posted anywhere else in this thread yet, so I figured I'd link to them:

Apple M1 Max with IHS cut away/removed and Intel Core I9-12900K die perched on top.

Actual photo of a real M1 Max die.

Close-up of UltraFusion link.

It looks like TechInsights may have finally published the first of their reports on the M1 Max shortly before the "Peek Performance" event, so hopefully some of that info will turn up in the public domain as well.

Also, the photo with the Alder Lake die in it strongly corroborates my latest round of die size estimates for the M1 family, so I'll include those here as well:

M1: 11.2 mm x 10.63 mm = 119 mm²
M1 Pro: 18.26 mm x 12.59 mm = 230 mm²
M1 Max: 18.26 mm x 21.36 mm = 390 mm²
M1 Ultra: 18.26 mm x 42.72 mm = 780 mm² (2x M1 Max)

 

[StinkyPinky]

Neat photos. Really is a fascinating time in the CPU industry. Huge leaps compared to the very stagnant period last decade. I vomit in my mouth a little bit when I think of quad core high end desktop cpus for an entire decade.

 

[soresu]

Nu ARM Neoverse core Demeter on the horizon...

Arm Posts GCC Tuning Patches For Neoverse-N2 & New Neoverse-Demeter - Phoronix

www.phoronix.com

The lack of news about Poseidon code makes me think Demeter is just a rename, likely corresponding to Neoverse V2 and by extension Cortex X3.

 

[soresu]

2.5 TBs in perspective.

pcie 4 = ~2 GBs per lane = 1250 lanes
pcie 5 = ~4 GBs per lane = 625 lanes
Infinity Fabric 3.0 = ~25 Gbs per pin, 16 pins per link 100 GB/s (50 bidirectional) = 25 Infinity Fabric 3.0 links

An instinct mi250 has 8 Infinity Fabric 3.0 links for a total of 800 GB/s (400 bidirectional)

M1 Ultra is 3.2x mi250

Yes but actually putting that in perspective, is there any chance it would ever need all that bandwidth unless there was some catastrophically bad bottleneck somewhere else in the design?

What is the actual number crunching figure of all those M1 Ultra constituent parts relative to a MI250?

 

[eek2121]

The M1 Ultra's GPU performance should put NVIDIA on notice. No, it doesn't beat a 3090 or even a 3080 in all workloads, however, the perf/watt is out of this world.

 

[Doug S]

The M1 Ultra's GPU performance should put NVIDIA on notice. No, it doesn't beat a 3090 or even a 3080 in all workloads, however, the perf/watt is out of this world.

Are there benchmarks for M1 Ultra yet?

Why should Nvidia care, even if the M2 based Mac Pro with its double the SoCs and more & better GPU cores is able to beat Nvidia's best? No matter how successful Mac Pro sales are by Apple's standards, it won't hurt Nvidia at all.

Would Ford care if Mercedes introduced a $150,000 car with better performance as well as better gas mileage?

 

[eek2121]

Are there benchmarks for M1 Ultra yet?

Why should Nvidia care, even if the M2 based Mac Pro with its double the SoCs and more & better GPU cores is able to beat Nvidia's best? No matter how successful Mac Pro sales are by Apple's standards, it won't hurt Nvidia at all.

Would Ford care if Mercedes introduced a $150,000 car with better performance as well as better gas mileage?

From ArsTechnica:

Spoiler

Unfortunately, no power consumption numbers for the GPU, however, for Handbrake the machine used around 87W of power. Not bad.

 

[Ajay]

From ArsTechnica:

Spoiler

View attachment 58754

View attachment 58755

View attachment 58756
View attachment 58757

Unfortunately, no power consumption numbers for the GPU, however, for Handbrake the machine used around 87W of power. Not bad.

I just read that. CPU single thread is strong and in line with current gen x86 CPUs. Multithreaded performance underwhelms a bit, no SMT may be the problem. Next year could be a problem if Apple doesn’t refresh. GPU performance looks appropriate to the likely Mac Studio's user base. Macs certainly aren’t primary targets for game developers and even less so with Metal on arm silicon. No upgradeable ram makes sense with DRAM on package. Lack of upgradeable M.2 SSD is a bit lame, but is probably a packaging issue. Actually reasonably specced for its price range. Could be a bit better, but while improving, Apple is still Apple.