Apple: G5's FSB really 1GHZ?

[foxkm]

Anyone know what kind of data bus the G5 system has? The top of the line supposedly has 1ghz speed, but we know how companies (amd/intel) distort that with DDR and QDR technology. If Apple is using QDR technology, then they are actually using a 250mhz FSB, which is impressive...

Anyone have the detailed specs?

 

[Xe0n]

Dont know the answer to your question, but I have one comment on their 1ghz fsb... Jobs says it is the "fastest fsb on any moden computer" or something along those lines at the WWDC Keynote (we have a few Ku and C band dishes at work, we watch all the apple keynotes). However, isnt the Opteron's fsb faster, given that it is technically at the same speed as the processor?

 

[Mingon]

It runs at half the processor speed, hence it scale through 800,900 and 1000 with the 1.6,1.8 and 2.0ghz power 5 chips

edit - the opteron processors are still limited by the speed of HT which is currently 800mhz iirc

 

[zephyrprime]

It's probably QDR 250. But I think Apple calling their bus 1000MHz is perfectly legitimate. I think it's dumb to perennially be pointing out stuff like "it really only 250mhz but it's quad pumped". Even if the timing clock is 250, the data rate is 1000.

 

[Mingon]

read this for more info


below snippit refers to 1.8ghz

When you combine the 970's 32KB d-cache with its sizable 512KB L2, its 900MHz DDR frontside bus and its support for up to 8 data prefetch streams, then you can see that this chip was made for floating-point- and SIMD-intensive media applications. It should go almost without saying that this chip will perform better on Altivec (or "VMX") code than the G4e just based on these features alone.

 

[Barnaby W. Füi]

Yeah, I was gonna say, it's just DDR, so whatever the quoted bus speed is, it's half that.

 

[imgod2u]

The "ElasticIO" bus on the PPC 970 is a serial point-to-point bus much like Hypertransport. It is 32-bit bidirectional and runs at 1/4 the processor clockrate (on the current model) using DDR signaling. At 500MHz (for a 2 GHz model), that's 3.2 GB/sec of bandwidth in each direction.

 

[SocrPlyr]

imgod2u... close, but assuming all your info is right the actually bandwidth is 4.0GB/s just re do the numbers... 32/8*500*2... the p4's bus runs a 3.2GB/s...

Josh

 

[addragyn]

Apple: G5's FSB really 1GHZ?

Yes, for the 2GHz model. FSB is 1/2 of CPU speed. So 1.8GHz has 900MHz bus.


Anyone have the detailed specs?

Try Apple. There is a ton of info in this thread. Check it out!


imgod2u... close, but assuming all your info is right the actually bandwidth is 4.0GB/s just re do the numbers... 32/8*500*2... the p4's bus runs a 3.2GB/s...

FSB bandwidth is 16 GB/s, RAM bandwidth is 6.4GB/s. From the following link.


The G5 uses a point to point architecture for each CPU, somewhat like Opteron. This is a more sophisticated design that is just now appearing on PCs (I mean that in the broadest sense). The FSB is not the same thing as the memory bus. It can be useful to have a FSB like this in the instance that disk, network, and RAM are working simultaneously. G5 architecture

 

[wetcat007]

Wow a must use a loooowww multiplyer..

 

[EdipisReks]

Originally posted by: wetcat007
Wow a must use a loooowww multiplyer..

4.

 

[foxkm]

Originally posted by: Mingon It runs at half the processor speed, hence it scale through 800,900 and 1000 with the 1.6,1.8 and 2.0ghz power 5 chips

edit - the opteron processors are still limited by the speed of HT which is currently 800mhz iirc

I think we have determined that the actual signaling rate is 1/2 the quoted bus speed. so its 400,450,500. This is still pretty damn impressive as anything directly attached to the main bus (ie North/south bridge) will be running that speed. My poor Athlon only has a true 200mhz FSB (400ddr)(on intel 800mhz qdr), which is the max for current intel/amd offerings.

Originally posted by: imgod2u The "ElasticIO" bus on the PPC 970 is a serial point-to-point bus much like Hypertransport. It is 32-bit bidirectional and runs at 1/4 the processor clockrate (on the current model) using DDR signaling. At 500MHz (for a 2 GHz model), that's 3.2 GB/sec of bandwidth in each direction.

Wouldn't a 64 bit System Bus be more logical as you are dealing with 64 bit cpu instructions, especially in dual CPU models?

 

[FishTankX]

That's technically incorrect.

For Intel processors, while the main bus may only run at 200MHZ QDR, the address bus, which infleunces latancy to a large degree, runs at 400MHZ. The address bus runs at twice the speed as the main data bus. Impressive, eh? The P4 can transfer addresses twice per clock.

Anyways, i'm far more concerned with L1 and L2 cache bandwidth, as those are huge influential factors.

Currently the Athlon has something like 1/4 the bandwidth of the P4 to L2. Actually, I think less than that. I remember there was a point at which the Palomino 2000+ had 1/5 the L2 bandwidth of the P4 2.0GHZ.

 

[Sunner]

The Athlon XP has a 64 bit bus to the L2, so at the same speed, the Athlon will have 1/4 the L2 bandwidth of a P4.
That is assuming the Athlon can transfer data on every cycle of course...not sure about that?

 

[FishTankX]

The Athlont transfers data every other cycle. Like the PIII.

 

[Eug]

The FSB is separate from the memory bus.

Memory bus is 800 MHz (dual channel DDR400).

The FSB is half the CPU speed. For a 2 GHz CPU it's 1 GHz.

However, there are other multipliers that can be used other than 2X. eg. If there were a 3.3 GHz G5, it'd probably use a 3X multiplier for an FSB of 1.1 GHz. (And memory would still be dual channel DDR400, unless faster memory became available.)

 

[Mingon]

Apparently they have problem currently with a fsb of much higher than 1ghz, so whilst a 1.1ghz fsb could be used, they might also rely on the 900mhz for other models with a higher speed.

 

[Eug]

Originally posted by: Mingon
Apparently they have problem currently with a fsb of much higher than 1ghz, so whilst a 1.1ghz fsb could be used, they might also rely on the 900mhz for other models with a higher speed.

Says who? I wouldn't doubt a say 1.25 GHz FSB might be difficult, but I haven't seen any info posted anywhere about this. It's moot anyway for now, since the top end CPU right now is 2 GHz.

Anyways, a 2X multiplier for a 1.25 GHz FSB would be a 2.5 GHz CPU.

For a 2.5 GHz CPU, a 3X multiplier would be an 833 MHz FSB.

I wonder if they have a 2.5X multiplier. That would give a 1 GHz FSB with a 2.5 GHz CPU.

IBM has only mentioned multipliers like 2X, 3X, 4X, etc. They haven't mentioned 2.5X, 3.5X, 4.5X multipliers, but nobody has asked. Having a 2.5X and 3.5X multiplier would certainly make the upgrade path a lot more flexible.

And just as a reminder, as I said, the memory speed is not an issue, since the memory bus doesn't have to run at the same speed as the FSB.