Anyone know why.... socket->slot->socket?

[Modeps]

Anyone know the specific reason that they converted back to socket based motherboards? I know that the original processors were socket based but I thought that they went to slot because it was better? I dont know! 🙂

 

[Dulanic]

Slot was used to get the cache closer to the die and run faster. Well now we can run cache 1:1 ON die so socket is king again.

 

[pillage2001]

ERm...Intel was the one who wanted to shift the the Slot1 technology. Later, they found out that it is costly and I think there's something bout the performance issue where the Level 2 Cache is faster only when it's on the die itself. It was another strategy to outbeat their competitors AMD. 😉

 

[wj]

Socket is cheaper to make, plus the new Socket chips has the L2 on the chip where as the Slot one chip had L2 on the slot. L2 on chip on need for the slot one. I think that why.



wj 😎 😎

 

[Noriaki]

Socket7: The L2 cache was on the motherboard and ran at FSB speed.

When CPUs started hitting getting fast this became very slow, a 200Mhz P55C ran the L2 cache at 66mhz..that's a 1/3 divider..remember what happened to AMD with teh classic athlon when it got it's 1/3 divider..the performance got choked out....sooo enter:

Slot1: The L2 cache is moved into the processor cartridge so it can run at 1/2 CPU speed and be much faster than the 66Mhz the FSB allowed (it would be 133 today, but that would still be horribly slow for a P3-1000)

This helped them alot for performance, but later it became evident that even 1/2 speed cache was to slow so they transferred it ondie to full speed. When they did this the PCB in the CPU cartridge no longer had anything on it but the CPU...so they transferred over to a new socket so that they could cut manufacturing costs, by not using that PCB and cartridge.

Thus we are now at Socket370.

Replace Slot1 with SlotA, and Socket370 with SocketA and you get the AMD story, it's much the same (so long as you ignore the K6-3, which had ondie cache already, but because it had massive 256k L2 and 64k L1 caches it was rather costly to produce on a .25um process, especially with the bad yeilds AMD was cursed with for the K6-x)

so P-MMX, P2/3, Coppermine or K6-2, K7, Tbird it goes Socket/Slot/Socket but each step increases cache speed.

 

[Modeps]

hey, thanks for the full out explanation! it just seemed odd to me that they would go back to what looked to be an antiquated solution, but its really not. 🙂
yeay fast cache!

 

[pm]

Note: this is my version of events - it may or may not have anything to do with reality

Designers began to realize after the Pentium processor that memory/processor communication performance was limiting overall system frequency. So the cache needed to be run at a faster frequency and have lower latency, but it also needed to be large enough to make a difference. So, Intel tried to use a technology called MCM (multi-chip module) - which was used in the Pentium Pro design. This put two chips into the same package and while still using a socketed design (socket 8, IIRC).

But this was very expensive to manufacture, so a new approach was needed. The cache needed to be very close the CPU in order to reduce latency and so that the frequency would be as high as possible, but actually putting it on die (at 0.35um and 0.25um) increased the production cost too high and left too little room to put enough cache on to matter. So, Intel introduced the slot design. This allowed the cache to be put very close to the processor and run at a high frequency (1/2 the core). It was not, IMO, an attempt to stop competition (who readily adopted the idea as well, if you recall), but merely a way to solve an engineering problem.

But the slot design introduced a whole pile of new issues for both the manufacturer (Intel and AMD) and the system designer (Dell, Compaq). 0.18um technology allowed enough cache to be put on die that the slot design was abandoned and we are back to socketed parts again.

So, the final answer: why socket -> slot -> socket? It was a temporay way to improve cache performance in the 0.35um and 0.25um process technologies where it was too costly to put this cache on the CPU die.