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Any thoughts on Palomino?

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ReMeDy: I do work for Intel. I'm a microprocessor circuit designer. As far as certification... I have an Master's in EE. Nutz has been hired but I don't think he's started yet (I keep meaning to email him and ask). As far as cost, yeah, I think it's above $30k. But I don't know, really, periodically my manager just comes by and says "How badly do you need an upgrade?" and I tend to reply "Well, I could get a lot more done with a faster machine, so put down 'badly'". And then I get a new one. My last machine was an HP C3600. Intel uses Sun, IBM and HP workstations.

If your comment about where I work was in relation to my commenting on Palomino, I imagine that I read as much about AMD as anyone else on here, and I'm probably more qualified than most at guessing how hard it would be to implement anything on real silicon. I'll add, however, that the last one, the bit about the cache doubling, is probably from someone who is mixing up Mustang and Palomino because I can't think that AMD would increase the cache size to 512K on a mainstream 0.18um part. For Mustang, it would have made sense but it would increase the cost of the part too much to put it on Palomino on 0.18um, IMHO.
 
Has anyone heard of AMD using isotopically pure silicon-28 for the palomino?

Apparently it transfer heat much better then normal silicon. There was a report awhile back about AMD demostrating a 1.5Ghz Palomino with a heat sink but no fan.

Is there any truth to the pure silicon?

If true wouldn't this be a big advantage compared to the P4.

Can you say quiet computer.

 
I am familiar with Isonics and their isotopically pure silicon - which, rumor has it, AMD has been considering. Although I agree with their fundamental premise - that isotopically pure silicon has better thermal conduction - I have two issues. The first is that the thermal conduction is not quite as good as claimed by Isonics (40% better than "natural" silicon @100C) when you actually measure it on a real CPU die. They are using bulk wafers with no actual devices on the wafer. In a real chip, the disruption of the lattice from ion implantation and other fab operations will result in a degraded lattice near the FETs (and to a lesser extent, within the substrate itself) no matter what type of silicon you use. The fact that the actual substrate has a clean lattice won't change the fact that near the devices that you need to cool, you have lattice defects. I would wager that in real devices, the effect of isotopically pure silicon is less than measured in the bulk wafers that they are referring to on their page.

But still, whether it's 20% better or 40% better - it's still better and I agree with this. The second problem that I have is supply - and I think this is the reason that no one to date has announced a product using istopically pure silicon wafers. Isonics is the only supplier that I know of and I doubt thier ability to produce a steady supply of wafers to any partner. This press release from their web page underscores the point. I'm not sure that anyone wants to count on them for supply until they are better proven (of course, this is a bit of a catch-22). AMD might consider them for mobile parts (volume is low, thermal conduction is more important).

Finally, there is cost. Isotopically pure silicon wafers cost between 50 and 100 times more than "normal" silicon wafers bought in volume ($0.20/wafer and $10/wafer - these numbers are based on some rumors that I heard though). Compared to the rest of the design and manufacturing process for chips, this is not an exorbitant amount, but it is definitely a consideration. And it's only really worth it if you can consistently avoid having to use more extravagant cooling techniques (if, for example, it cuts the power of your chip from 140W to 100W and you can thus avoid having to use active cooling techniques such as refrigeration). If it cuts power from 50W to 40W then it's not really worth it at all.

Lastly, it's worth noting that no one that I'm aware of is using Isonics wafers in their production units and no one (again, that I'm aware of) is committed to using them in the future.
 
Pm, thanks for the explanation, if I may impose one more question.

From the press release.
``I would like to clearly state that this delay does not impact our epitaxial wafer program. We have sufficient isotope in inventory and the ability to procure substantially more from our current supplier to continue supplying sample wafers and to ramp up to production levels.''

Since the pure silicon is only in a small layer wouldn't that increase the ability of the company to produce wafers on a production scale?

$10 per wafer does not sound like much of an added cost.

I was about to ask about epitaxial until I found their faq
 
Etch - I apologize if I sound formal in my messages. I spent too many years living in England and picked up a bit of the British style of writing. Anyway, feel free to impose any questions - and email if I don't make any sense. 🙂

So, Isonics make two types of wafers. Bulk silicon isotopically pure wafers - which is what I was talking about - and isotopically pure epitaxial wafers. A "bulk silicon wafer" means that the entire wafer is made from the same material, while expitaxial wafers are made by taking a bulk silicon wafer and depositing a thin layer (called the expitaxial layer) on top of the wafer. Most (all?) modern wafers are expitaxial wafers. You start with a wafer doped to a certain concentration of dopant and then you deposit the real substrate for the devices onto this wafer using an expitaxial layer. So, what they are talking about is making this deposited layer isotopically pure.

But the difference between expitaxial isotopically pure wafers versus a bulk isotopically pure wafer is that the former doesn't improve the thermal dissipation of the actual wafer - but only of this thinly deposited layer. So the chips thermal properties are unchanged, but the thermal characteristics of the invididual transistors are improved. So if you have a local "hot spot" on the chip - for example, a wide pseudo-NMOS OR gate - you can dissipate some of the heat of this hot spot over a broader area. This should result in slightly faster circuits and, since the reason that hot-spots occur is that people need a high-power circuit to make timing and since heat will slow down the operation of this high-power circuit, it could improve the overall frequency that the chip can be run at.

This is enough of a stretch that I'm not sure I believe their PR on this though. I think I'd need to see real experimental results. In my experience, it's not that there's one individual "hot spot" and a whole lot of cool stuff around it. Usually, the caches are cool, the control logic is warm and the custom datapath logic is hot. The datapath portion is usually grouped tightly together (to avoid wiring delay) and I can't believe that a thin expitaxial layer will do more than improve the characteristics of the datapath circuitry on the ends of a circuit (so, bits 0 and 63 of a 64-bit adder might be somewhat cooler, but bits 31 and 32 in the middle of the datapath are unchanged).

But, anyway, these epitaxial isotopically pure wafers won't help at all with dissipating heat off of the chip itself - only locally. So, if anyone wants to use this pure silicon to, for example, remove the fans from their CPU then they need to use bulk silicon wafers - which where my concerns about supply come in.

And you are right about the cost. It's not much compared to the overall cost of the design and the fab itself (plus the workers). But still if, for example, you are doing 2000 wafer starts per week, then using isotopically pure silicon will cost at least $1 million more per year over bulk silicon. Compared to the other costs, this isn't enormous, but it's still significant..
 


<< I do however agree that most people do not need anything faster than a p 233mmx >>


I hope you are kidding, I think 500mhz should be the lowest these days. Have you ever used ie5.5 on a p233mmx? its a joke.



<< i dont care how good heat is transferred, no new CPU will/should run in a comp without any fans. >>



Have you looked at the new mobile chips? Apple? The new palamino was rumoured to have the istonic silicon or whatever it is and its suppose to reduce heat 90%. (not fact, no need to flame) and if thats true, screw the fans. Quiet PC here i come.
 
Noxipoo:



<< The new palamino was rumoured to have the istonic silicon or whatever it is and its suppose to reduce heat 90%. (not fact, no need to flame) >>



Did you read any of what I wrote about this technology in the last couple of posts that I put up? Not a flame - I'm just curious. I practically wrote an essay on the technology (as I understand it, anyway).

Even the guys making the wafers don't claim anywhere near 90% reduction. They are claiming 40% and I think even that is too high for the reason that I stated previously.
 
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