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Answer for this sample A+ question

joohang

Lifer
I found today's ExamCram.com A+ question of the day quite interesting.

Optimum L2 cache in most systems is _____.

A) 128K
B) 256K
C) 512K
D) 1.2MB

I said 512K, thinking that "most systems" would be Pentiums and P2's. What do you say?
 
Jalapeno,

That's the reason why I chose 512K.
If I recall correctly, the Pentiums had 512K pipeline burst cache. I belive that P2's also had 512K cache.
 


<< If I recall correctly, the Pentiums had 512K pipeline burst cache >>


the katmais had 512Kb of off-die L2 cache running at half the bus speed.
the coppermines have 256Kb of on-die L2 cache running at full bus speed.
 
bacillus,

When I said &quot;Pentiums&quot; I meant the original Pentiums. The so-called &quot;Pentium I's.&quot;
 
Here's the answer I got in e-mail today:

Answer c is correct. The L2 cache is the external cache for the CPU and helps improve CPU performance significantly. Many low-end systems provide only 128K of cache. This might be adequate, but with heavy use the system might experience unexplainable performance slowdowns. Many entry-level systems also include 256K of cache. This seems to work well for many applications, but if you really want to turn your CPU loose, 512K seems to be optimum. Beyond 512K, the system performance might improve, but not as dramatically as the move from 128K to 256K or from 256K to 512K.

===

I guess that us Anandtechers think too much. I was more concerned whether it was on-die full-speed cache or not. 🙂 And wonder how this explains Duron's superb performance. A+ exam must be quite outdated. That response sounds like the computer world 5 years ago.
 
It's a little ridiculous when a VLSI designer from a CPU design company who designs CPU caches for a living (ie. me) get's a question like this wrong.

That question is way outdated: it's vintage 1995 - and even then it ignores everything outside of the consumer desktop market.

That question is also very poorly worded. It doesn't say under what instruction architecture, it doesn't mention the size of the application or the dataset, it doesn't menion the cache line size, and it makes no mention of the estimated hit rate of the cache.

Fine, I design CPU caches for living and so I'm being a little picky, but this is supposed to be a high-tech certification exam - the guys posing the questions should understand the issues enough to ask detailed questions, either that or they shouldn't ask them at all.

If the question had been: &quot;The optimal L2 cache size on a Pentium based system running a general purpose OS in a non-server environment is:&quot; then the question would have been merely outdated rather than deceptive.
 
I see your points.

I hate vague questions. MCP exams allow me to write &quot;disputes&quot; and add some writing to unclear questions. Do A+ exams do that?
 
Optimum cache size depends on workload and external memory performance.
From Hennesy/Patterson, the average memory hierarchy access throughput is:
p*cache_throughput+(1-p)*mem_throughput, where p is a cache hit ratio.
The same formula is used to calculate the average memory access latency.
Since the relative memory latency increase (and throughput decrease) with each
successive CPU generation, better hit ratio is needed. As a rule of thumb,
2x cache size increase decreases cache miss ratio by half. Also, more asociativity provide better hit rate.

Cache size is also dictated by the die size constraints, since bigger die tremendously increases production costs.

Bottom line: for current desktop applications 256K 8-way set-associative cache looks enough, however for future CPUs cache size requirements may well increase.
 
this question is ridiculous. you might as well ask how long is a piece of string. you cannot ask vague and open questions like that. if such questions are representative of your course and exam then i would be disturbed.
is this A+ worth anything then?
 
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