AnandtechAMD Carrizo ExcavatorReview

[Phynaz]

Since i have seen Phynaz post through another post i will adress his statement..

For one when i say 128 bit i perfectly know that there s a parity bit added per Byte, i say 128 to keep things easy to understand.

Second is that RAM do not use differential signals, otherwise 128 wires (+ parity bits) would be necessary per dimm, indeed i invite him to check the pin out of a RAM module..

http://www.simmtester.com/page/news/images/dimm/ddr3%20dimm%20pinout.jpg

http://www.simmtester.com/page/news/showpubnews.asp?num=170

http://www.samsung.com/semiconductor/global/file/product/ds_ddr3_4gb_b-die_based_rdimm_rev15-0.pdf

Each bit is conveyed relative to the ground as reference, in a differential wiring there s a + signal and a - signal that are both referenced to the ground but the receiver just use the difference between the +- signals, this allow to almost anihilate the parasistic signals (noise) that could be induced in the transmission lines.




Fact is that once the MB is manufactured the cost to solder a Carrizo or a Carrizo-L is the same, the only difference between the two laptops is the APU price delta as well as a negligible difference in the APU power supply.

Actualy the difference will be on the screen and other customisable features since 1080p for instance are used only for Carrizo if we except a HP C-L laptop...

All wrong.

64 bit DDR is broken into eight 8_bit lanes, with strobe and data mask added. There is no parity on the data.

As far as differential signaling, all clock signals are differential. As a matter of fact one of the purposes of the DIMM is to provide differential signal termination.

As you were asked in another thread and failed to respond, what is your education and what do you do for a living?

I give you credit for succeeding in derailing another AMD thread.

 

[Phynaz]

+1 that defenders should be doing that. In this case it was a typical result of little time and not so clear statements.

As I have to keep my spare time down (being 40, with children soon), which also means, I have to manage where I put my time, I still prefer to do research about future tech.

Children? Congrats!

 

[MrTeal]

Since i have seen Phynaz post through another post i will adress his statement..

For one when i say 128 bit i perfectly know that there s a parity bit added per Byte, i say 128 to keep things easy to understand.

Second is that RAM do not use differential signals, otherwise 128 wires (+ parity bits) would be necessary per dimm, indeed i invite him to check the pin out of a RAM module..

http://www.simmtester.com/page/news/images/dimm/ddr3%20dimm%20pinout.jpg

http://www.simmtester.com/page/news/showpubnews.asp?num=170

http://www.samsung.com/semiconductor/global/file/product/ds_ddr3_4gb_b-die_based_rdimm_rev15-0.pdf

Each bit is conveyed relative to the ground as reference, in a differential wiring there s a + signal and a - signal that are both referenced to the ground but the receiver just use the difference between the +- signals, this allow to almost anihilate the parasistic signals (noise) that could be induced in the transmission lines.

The signals in those simmtester links you posted with a / in front of them are the active low signals. When you see pins 63 and 64 labeled CK1 and /CK1, that's a differential signal. Phynaz never said all the data lines were differenetial, just that he could think of a half dozen of them. If you look at your link, you'll see fifteen differential signals.

This whole debate is silly, to the point I have to wonder what your intentions are. The Stilt's point before you started derailing the thread was pretty simple; in an FP4 system with two DIMMs you could either connect them both to memory channel A allowing you to use both slots with both processors but only in single channel mode, or you could connect one DIMM to each of channel A and channel B, giving dual channel operation to Carrizo but only the ability to use a single slot to Carrizo-L.

 

[Phynaz]

Thank you Mr Teal

 

[Shaun_Brannen]

+1 that defenders should be doing that. In this case it was a typical result of little time and not so clear statements.

As I have to keep my spare time down (being 40, with children soon), which also means, I have to manage where I put my time, I still prefer to do research about future tech.

Understandable

Sorry for the passive-aggressive douchiness.

 

[Arachnotronic]

As I have to keep my spare time down (being 40, with children soon), which also means, I have to manage where I put my time, I still prefer to do research about future tech.

Congratulations! Hope they bring you lots of joy

 

[The Stilt]

Any specific tests in this review you would like to see retested on a proper system?

 

[el etro]

Any specific tests in this review you would like to see retested on a proper system?

ShortForm, Linux and iGPU benches sir!

 

[Abwx]

The signals in those simmtester links you posted with a / in front of them are the active low signals. When you see pins 63 and 64 labeled CK1 and /CK1, that's a differential signal. Phynaz never said all the data lines were differenetial, just that he could think of a half dozen of them. If you look at your link, you'll see fifteen differential signals.

This whole debate is silly, to the point I have to wonder what your intentions are. The Stilt's point before you started derailing the thread was pretty simple; in an FP4 system with two DIMMs you could either connect them both to memory channel A allowing you to use both slots with both processors but only in single channel mode, or you could connect one DIMM to each of channel A and channel B, giving dual channel operation to Carrizo but only the ability to use a single slot to Carrizo-L.

It was clear that i said that the data bus doesnt use differential signal, so no need to ask me what my intentions are since you re not even quoting me accurately...

To get back on topic there s no single channel Carrizo laptop other than by the fact that they are delivered with a single RAM module..

I also provided data that show that the single laptop tested by AT that was using this configuration, the Toshiba, was a sample and that the actualy commercialised product has two channels.

All this single channel myth is just fud from the usual suspects, i saw no one here pointing that lots of laptops using SKL are single channel since there s only one ram module in the laptop, curiously nothing about this, yet such laptops exist in big numbers, just check here :

https://geizhals.de/?cat=nb&xf=6752_Core+ix-6xxxU#xf_top


Edit : The Carrizo laptops, even the cheaper one has dual channel...

https://geizhals.de/?cat=nb&xf=6749_13#xf_top

http://www.notebookcheck.net/HP-Pavilion-15-ab052ng-Notebook-Review.152289.0.html

 

[coercitiv]

To get back on topic there s not single channel Carrizo laptop other than by the fact that they are delivered with a single RAM module..

Dell thinks otherwise.

 

[hojnikb]

Are we gonna get Athlon x4 845 review anytime ?

I do wonder how it performs in games coupled with a mid tier gpu like 950/370 or even 960/380.

 

[MrTeal]

It was clear that i said that the data bus doesnt use differential signal, so no need to ask me what my intentions are since you re not even quoting me accurately...

To get back on topic there s no single channel Carrizo laptop other than by the fact that they are delivered with a single RAM module..

I also provided data that show that the single laptop tested by AT that was using this configuration, the Toshiba, was a sample and that the actualy commercialised product has two channels.

All this single channel myth is just fud from the usual suspects, i saw no one here pointing that lots of laptops using SKL are single channel since there s only one ram module in the laptop, curiously nothing about this, yet such laptops exist in big numbers, just check here :

https://geizhals.de/?cat=nb&xf=6752_Core+ix-6xxxU#xf_top


Edit : The Carrizo laptops, even the cheaper one has dual channel...

https://geizhals.de/?cat=nb&xf=6749_13#xf_top

http://www.notebookcheck.net/HP-Pavilion-15-ab052ng-Notebook-Review.152289.0.html

You clearly said the data buses don't use differential signalling?

It is clear, it s you that are inventing random explanations to sustain an unsustainable point since you dont understand what is exactly an electronic circuitry, the fact is that RAM buses dont use differential signals so there s only 64 wires for 64 bit.

The 294 pins are for four dimms, each dimm use a 64 bit bus, the four buses are then paired with a dispatcher, same as Carrizo-L but with four dimms and two channels....

If only two dimms are used then Carrizo will use two relevant 64 bit paths, as said there s a 64 bit transmitter per dimm, including in Carrizo..

Sounds like you said RAM buses don't used differential signals, coincidentally because that's exactly what you wrote. Modern DDR RAM buses do use differential signalling.


Can you please provide a source for that quote, which seems to be the basis of all the issues here. You said Carrizo uses four 64 bit paths for four DIMMs with some kind of internal dispatcher, which is just wrong.

Let me explain it simply since you confuses adresses and pin count...

Carrizo has 128 pins for the dual channel data bus (plus the parity bits), lets call them pin0-127.

If Carrizo L is to be compatible in the same MB then it means that it has 128 pins as well for the RAM, difference is that the 128 pins are going to a dispatcher (inside the APU as said ad nauseam) that select either the pin0-63 or the pin64-127 at clock rate and dispatch the relevant RAM DIMM to an effective 64 bit bus.

Indeed Kabini support 32GB and designing a MB that can support 4 or even 2 dimms within a single channel and in parrallel mode is not an easy task (see the X99 plateform and its 4 slots/channel...), it is much better to use two 64 bit transmitters rather than a single one, the transistor cost is extremely small while this increase the max frequency of the transmissions lines (traces on the PCB that convey the signals).

Any source at all for that Carrizo L has 128 pins for the RAM data buses and some kind of internal dispatcher that connects the internal controller to and external bus?

 

[eRacer]

This whole debate is silly, to the point I have to wonder what your intentions are.

His intent is to "prove" that the Anandtech Carrizo article is nothing more than a viral marketing hit piece to promote Intel.

 

[USER8000]

Edit : The Carrizo laptops, even the cheaper one has dual channel...

https://geizhals.de/?cat=nb&xf=6749_13#xf_top

http://www.notebookcheck.net/HP-Pavilion-15-ab052ng-Notebook-Review.152289.0.html

Wait,what??

They sent out models with single channel memory and this model which is 450 Euro has dual channel memory.

AMD MARKETING EPIC FAIL.

 

[Abwx]

You clearly said the data buses don't use differential signalling?

Sounds like you said RAM buses don't used differential signals, coincidentally because that's exactly what you wrote. Modern DDR RAM buses do use differential signalling.

No, a bit use a single wire referenced to the ground, at the end i m tired posting the same links :

http://forums.anandtech.com/showpost.php?p=38013920&postcount=174

A truly differential signal use two wires per bit, you cant use a common reference for all bits, this would destroy the purpose wich is noise immunity.

Can you please provide a source for that quote, which seems to be the basis of all the issues here. You said Carrizo uses four 64 bit paths for four DIMMs with some kind of internal dispatcher, which is just wrong.

Any source at all for that Carrizo L has 128 pins for the RAM data buses and some kind of internal dispatcher that connects the internal controller to and external bus?

There are AMD pdf datasheets available with the pins functions.

 

[MrTeal]

No, a bit use a single wire referenced to the ground, at the end i m tired posting the same links :

http://forums.anandtech.com/showpost.php?p=38013920&postcount=174

A truly differential signal use two wires per bit, you cant use a common reference for all bits, this would destroy the purpose wich is noise immunity.

That's pretty random, since I said nothing about that and it avoids the whole point. You clearly said that ram buses don't use differential signalling (which the do, just not on data), and then got pissy when someone called you on it and claimed you clearly said the data buses don't use differential signally (when you didn't). No one here is arguing that the data lines are differential.

There are AMD pdf datasheets available with the pins functions.

I'd love to read through the FP4 socket design specification. I've read through the AM2 and AM3 ones awhile ago, but can't seem to find FP4 listed on AMD's site or the broader internet anywhere.

 

[Abwx]

Wait,what??

They sent out models with single channel memory and this model which is 450 Euro has dual channel memory.

AMD MARKETING EPIC FAIL.

They sent nothing, they invited Ian Cutress at AMD where a few early samples laptops were put at his disposal, prove is that the Toshiba he tested has actual single channel while the one actualy sold has two channels.


As for RAM deliveries a lot of laptops, as shown by the links i posted, have only one delivered but they should be dual channel, at least for AMD as Intel s based Lenovo Yoga 700 is apparently an actual single channel laptop...

http://www.expertreviews.co.uk/lapt...1in-review-different-yoga-same-flaws/page/0/1

 

[Dresdenboy]

Congratulations! Hope they bring you lots of joy

Understandable

Sorry for the passive-aggressive douchiness.

Children? Congrats!

Thanks guys. Of course we start with 1, but this is just the beginning.

 

[ShintaiDK]

His intent is to "prove" that the Anandtech Carrizo article is nothing more than a viral marketing hit piece to promote Intel.

LOL!

 

[Sweepr]

His intent is to "prove" that the Anandtech Carrizo article is nothing more than a viral marketing hit piece to promote Intel.

Saddest part is, he is not the only one:

A correction, AMD supplied laptops fulfilling some requisites from Inteltech that we don't know.

In my opinion they shouldn't supply any product to Inteltech, especially cpus or apus because of past experiences and because the current article is the best example of how things are conducted there:

- As a review or comparison of laptops or systems it is extremely bad, perhaps the worst I've seen in a long time.
- Inteltech says they want to test if the claims made by AMD on the Tech day were true but they don't test similar conditions, perf/w, etc. A lot of blah, blah, blah for nothing.
- As a comparison of cpus it fails, they are tested under very different conditions, different OS, different HDD SDD, different memory configurations, etc. Any conclusion made is a complete waste of time and only food for idiots.
- What was said about cpus can be said again for igpus or dgpus.
- If we talk about OEMS the article is based on a few system configurations that apparently Inteltech wanted. In a proper article the author would investigate what the OEMs are selling and what is lacking in the market or what is bad with those offerings, but this would take a lot of boring time browsing and perhaps calling OEMS, obviously it is much more fun to call, travel and meet some AMD's engineers, have some talks, drinks,etc.
The article lacks credibility, it's badly documented, etc... but it gets worse, with all this burden the author feels encouraged to throw some theories and solutions into the mix when we don't know his background or experience on this field. Bah, as the article is disguised as something intelligent fools will feel enlightened.

All of that with the usual Inteltech stuff, in the second paragraph they are already talking about how good was an Intel SOC in a product they tested some time ago.

Now let me ask you,
What do you think about this long mix of things called article or review or whatever?
To whom does it cater? People searching laptops? OEM Executives? AMD executives? People interested on cpu differences or improvements?...

http://semiaccurate.com/forums/showpost.php?p=254320&postcount=1274

SA never fails to make me laugh.

 

[Arachnotronic]

Saddest part is, he is not the only one:



http://semiaccurate.com/forums/showpost.php?p=254320&postcount=1274

SA never fails to make me laugh.

S|A forums are basically AMDZone Redux.

 

[USER8000]

They sent nothing, they invited Ian Cutress at AMD where a few early samples laptops were put at his disposal, prove is that the Toshiba he tested has actual single channel while the one actualy sold has two channels.


As for RAM deliveries a lot of laptops, as shown by the links i posted, have only one delivered but they should be dual channel, at least for AMD as Intel s based Lenovo Yoga 700 is apparently an actual single channel laptop...

http://www.expertreviews.co.uk/lapt...1in-review-different-yoga-same-flaws/page/0/1

Wait,what he was at AMD and they didn't even give him production representative laptops??

This is the day whatever little faith I had left in AMD marketing just died.

 

[Phynaz]

His intent is to "prove" that the Anandtech Carrizo article is nothing more than a viral marketing hit piece to promote Intel.

Haha. With testing done in AMD labs with AMD provided systems. We all knew that AMD's marketing team sucks, but I didn't know they were working for Intel

 

[USER8000]

Haha. With testing done in AMD labs with AMD provided systems. We all knew that AMD's marketing team sucks, but I didn't know they were working for Intel

I think Intel should just pay AMD marketing instead - they seem to be able to market Intel laptops better than Intel can!!

 

[mrmt]

Haha. With testing done in AMD labs with AMD provided systems. We all knew that AMD's marketing team sucks, but I didn't know they were working for Intel

I wonder who will be the last of the faithful. Even our resident AMD reseller is trashing AMD these days.