[Anandtech] Intel's Architecture Day 2018

[PeterScott]

Intel's Architecture Day 2018: The Future of Core, Intel GPUs, 10nm, and Hybrid x86

I know some bits of this were getting some mention in other threads, but it seems like it was big enough to warrant it's own discussion.

Highlights for me were a new architecture (finally) Sunny cove, that looks to have potential (4-5 wide allocation) to deliver Intels first real IPC improvement in MANY years, and also what should be a nice improvement in the the IGP, and a look at Intels multichip solutions(Foveros) and Intel Big-little.

The Q&A was also somewhat interesting, like where they admit being node-locked on their designs really messed them up, and they will be more node agnostic in the future.

Overall, more actual news than we have seen from Intel in some time.

 

[PeterScott]

I'm amazed nobody is seeing what is laid right in front of them.

First, they introduce sunny cove specifically as an architecture independent from it's intended product (icelake).
Second, they mention how they have worked to decouple architecture from process.

Do you really think they would announce this if sunny cove isnt the first example of this? why introduce architecture names for ice lake if this decoupling hasn't occured already?
Why announce all this and not ship products for it beyond mobile which everybody _still_ expects on 10nm. Do you think they'd announce this if there isnt a first example a full year from now?

if it isnt clear to you (and jpiniero especially) sunny cove is a defacto announcement of ice lake architecture on 14nm I dont'know what is.

Willing to take bets sunny cove will appear on desktop next year with you jpiniero. Mind you, not talking about the process node it will ship with.

I don't see that at all. Where are you seeing Sunny Cove is decoupled from process node. Intel acknowledged that being node locked on newer design (presumable on Sunny Cove), is why they didn't have a faster 14nm design. They want to be more node agnostic in the future, but I don't see that as Sunny Cove.

Sunny Cove contains the architecture speedups that would have arrived sooner if 10nm had arrived sooner. I still don't expect them anywhere except in 10nm.

 

[jpiniero]

Anyone want to guess at what the "Cache Redesign" in Willow Cove is? To me it sounds meshy.

BTW, assuming:
Sunny Cove is Tigerlake's Core now used for Icelake and Lakefield
Willow Cove is Alder Lake's Core used for Tigerlake primarily
Golden Cove is Meteor Lake's Core

 

[Yotsugi]

"Child of Volta" - compute only - is surely very likely for 2019?

Very unlikely because they need enough N7 to beat 815mm^2 monstrosity.
I doubt 600mm^2 N7 dies are yieldable before 2020.

want to guess at what the "Cache Redesign" in Willow Cove is? To me it sounds meshy.

Can be literally anything, ICL itself has redesigned caches.

BTW, assuming:
Sunny Cove is Tigerlake's Core now used for Icelake and Lakefield
Willow Cove is Alder Lake's Core used for Tigerlake primarily
Golden Cove is Meteor Lake's Core

Nah, it's Icelake/Tigerlake/Alderlake.

 

[Qwertilot]

Announced maybe? They won't need sensible yields for the supercomputer parts etc.

iirc It took v100 a long time to drift down to anything other than that.

 

[Yotsugi]

Announced maybe? They won't need sensible yields for the supercomputer parts etc.

Genuinely no idea.
Perlmutter will use Milan + post-Volta, but that's a late 2020 system.

 

[IntelUser2000]

By the way,

Sunny Cove is a disappointment.

Compare what Skylake had to change to get 5-10% over Haswell. Then look at Sunny Cove vs. Skylake. After nearly 5 years we'll get another 5-10%.

Good times may be coming for AMD with Zen 3. If its really 10-15% faster per clock they might totally close perf/clock gap with Icelake.

Sunny Cove is starting to remind me of Netburst. Netburst's flaw was that it strove for clocks above all else, and they needed to abandon that. Sunny cove, because expanding upon Sandy Bridge is getting old. No new ideas, just more and bigger.

 

[Tuna-Fish]

Sunny Cove is a disappointment.

Compare what Skylake had to change to get 5-10% over Haswell. Then look at Sunny Cove vs. Skylake. After nearly 5 years we'll get another 5-10%.

In terms of IPC increase, I'm not so sure at all. Today, Skylake execution core is often wider than what the frontend and retire can support. It could be that most of the potential IPC increase of Skylake is basically gated on not being able to rename/retire more than 4 ops per clock. Widening those paths could alone mean a lot of extra IPC for tight loops that have great ILP. Two stores per clock is also a great boost, and one that I would not have expected. +50% L1d is also big.

I certainly expect substantially more IPC gain than from Skylake. To temper that somewhat, the widened rename and the increased L1d size both spell out "relaxed clock targets" to me.

 

[Spartak]

By the way,

Sunny Cove is a disappointment.

Compare what Skylake had to change to get 5-10% over Haswell. Then look at Sunny Cove vs. Skylake. After nearly 5 years we'll get another 5-10%.

Good times may be coming for AMD with Zen 3. If its really 10-15% faster per clock they might totally close perf/clock gap with Icelake.

Sunny Cove is starting to remind me of Netburst. Netburst's flaw was that it strove for clocks above all else, and they needed to abandon that. Sunny cove, because expanding upon Sandy Bridge is getting old. No new ideas, just more and bigger.

?

Sounds to me you have no clue what these changes entail when you compare it to Netburst.
The core will be wider not deeper, with optimised front-end to make better use of the execution units. Where you get 5-10 % is another mystery.

 

[itsmydamnation]

In terms of IPC increase, I'm not so sure at all. Today, Skylake execution core is often wider than what the frontend and retire can support. It could be that most of the potential IPC increase of Skylake is basically gated on not being able to rename/retire more than 4 ops per clock. Widening those paths could alone mean a lot of extra IPC for tight loops that have great ILP. Two stores per clock is also a great boost, and one that I would not have expected. +50% L1d is also big.

I certainly expect substantially more IPC gain than from Skylake. To temper that somewhat, the widened rename and the increased L1d size both spell out "relaxed clock targets" to me.

I've been wondering about the Store ports, would more store bandwidth mainly be a benefit to SMT? I've always thought you want to keep things in the store Que for as long as possible for store to load forwarding but i've never seen/heard of store being on the critical path. But with more rename/uop's a cycle and two threads to use them then i can see Store bandwidth being an issue.

 

[Tuna-Fish]

I've been wondering about the Store ports, would more store bandwidth mainly be a benefit to SMT? I've always thought you want to keep things in the store Que for as long as possible for store to load forwarding but i've never seen/heard of store being on the critical path. But with more rename/uop's a cycle and two threads to use them then i can see Store bandwidth being an issue.

Yeah, that part is really weird to me. To put it frankly, if you'd asked me before the event, I'd have said it's more likely they'd add a third load port than a second store port. I do a lot of instruction profiling, and I very rarely see code that is actually store-limited. Mostly badly optimized SIMD intrinsics code that ends up doing a lot of useless stores. Maybe?

 

[VirtualLarry]

Yeah, that part is really weird to me. To put it frankly, if you'd asked me before the event, I'd have said it's more likely they'd add a third load port than a second store port. I do a lot of instruction profiling, and I very rarely see code that is actually store-limited. Mostly badly optimized SIMD intrinsics code that ends up doing a lot of useless stores. Maybe?

Maybe something to do with AVX2-related Scatter/Gather support? Just a shot in the dark, I'm not so totally up on these micro-arch details. Though I like to read about them.

 

[Arachnotronic]

Anyone want to guess at what the "Cache Redesign" in Willow Cove is? To me it sounds meshy.

BTW, assuming:
Sunny Cove is Tigerlake's Core now used for Icelake and Lakefield
Willow Cove is Alder Lake's Core used for Tigerlake primarily
Golden Cove is Meteor Lake's Core

Sunny Cove -> Ice Lake
Willow Cove -> Tiger Lake
Golden Cove -> Alder Lake

 

[Arachnotronic]

By the way,

Sunny Cove is a disappointment.

Compare what Skylake had to change to get 5-10% over Haswell. Then look at Sunny Cove vs. Skylake. After nearly 5 years we'll get another 5-10%.

Good times may be coming for AMD with Zen 3. If its really 10-15% faster per clock they might totally close perf/clock gap with Icelake.

Sunny Cove is starting to remind me of Netburst. Netburst's flaw was that it strove for clocks above all else, and they needed to abandon that. Sunny cove, because expanding upon Sandy Bridge is getting old. No new ideas, just more and bigger.

Did Intel share the average IPC uplift number with you?

 

[IntelUser2000]

Yeah, that part is really weird to me. To put it frankly, if you'd asked me before the event, I'd have said it's more likely they'd add a third load port than a second store port. I do a lot of instruction profiling, and I very rarely see code that is actually store-limited. Mostly badly optimized SIMD intrinsics code that ends up doing a lot of useless stores. Maybe?

How much do you figure it'll gain? I'd have thought more loads would be better too. It doesn't sound like anything special. It's more of the same + making some corner case scenarios better.

Intel's very good architectural advancements resulted in 15-20%. Those were cores that took 4-5 years to arrive. The A12 is in SPEC, more than 30% faster at the same clock. You might make the argument that Intel cores clock higher, which is not really an advantage because they've hit the 5GHz ceiling that starts requiring exotic cooling to run.

2.4GHz Apple cores outperform 4GHz Intel cores. Think about that.

The core will be wider not deeper, with optimised front-end to make better use of the execution units. Where you get 5-10 % is another mystery.

I did not say it was Netburst. Netburst basically stood still since its incarnation. How much better do you think it'll do? 10-15%?

Pentium III to Pentium M: 30%
Core Duo to Core 2 Duo: 20%
Penryn to Sandy Bridge: 15%

Yea, no I'm not seeing anything amazing here after nearly 5 years.

Look in terms of historical gains. How much had to be done to get the 5-10% we got for Skylake. https://www.anandtech.com/show/9483/intel-skylake-review-6700k-6600k-ddr4-ddr3-ipc-6th-generation

Again, that's against Haswell, not Broadwell.

Did Intel share the average IPC uplift number with you?

No. However, let me ask you this: Do you think it'll be substantially better than 10-15%?

Let me ask you another question: How is a 10-15% best case scenario fine 5 years after Skylake, and with a 3 year delay? Especially in light of competition? And let's not bury our head in our sands and pretend Apple cores don't exist.

 

[jpiniero]

I did not say it was Netburst. Netburst basically stood still since its incarnation. How much better do you think it'll do? 10-15%?

Yeah, 10-15% compared to Skylake, but the U/Y parts might have a decent frequency improvement at base and similar at turbo as well.

 

[IntelUser2000]

Yeah, 10-15% compared to Skylake, but the U/Y parts might have a decent frequency improvement at base and similar at turbo as well.

I don't see anything better than normal coming with Sunny Cove. We're at the point of diminishing returns on everything. You get less returns for doing more work.

Even 5-10% is fine, if Icelake was 2017. We might see tiny -Y chips sneak by at the holiday 2019 timeframe, with most Icelake in 2020.

 

[Arachnotronic]

I don't see anything better than normal coming with Sunny Cove. We're at the point of diminishing returns on everything. You get less returns for doing more work.

Even 5-10% is fine, if Icelake was 2017. We might see tiny -Y chips sneak by at the holiday 2019 timeframe, with most Icelake in 2020.

Intel hasn't even disclosed all of the key microarchitectural details of Sunny Cove (e.g. the sizes of those buffers). How can you make such a precise IPC guess?

 

[jpiniero]

I don't see anything better than normal coming with Sunny Cove. We're at the point of diminishing returns on everything. You get less returns for doing more work.

You have to remember that it's essentially 3 generations of chips - Cannonlake, Icelake's original version and now Sunny Cove.

I figure there will be just that one die (with 4C+64 EU) but they will yield and quality bin it as hard as they can. Which is fine, given that Comet and Whiskey will be the vast majority of sales even in 2020. The marketing on this is going to be something.

 

[IntelUser2000]

Intel hasn't even disclosed all of the key microarchitectural details of Sunny Cove (e.g. the sizes of those buffers). How can you make such a precise IPC guess?

We don't have an awful big of a range to work from in the first place. The best gain we saw gen-on-gen was 30% in the past 20 years. That was back in the glory days of scaling and when desktop CPUs were using less power than laptop CPUs do today. So they had room to grow.

2019: Clock speed wall, low hanging fruit picked for ILP, TDP wall, diminishing returns in process, increasing costs

They've got lot of work to do just to get 10% nowadays. More work, for less gains.

Again, look at how much Skylake had to change. Everything is relative. Back in 2017 it would have been acceptable. In 2020 that's a whole different story.

 

[epsilon84]

We don't have an awful big of a range to work from in the first place. The best gain we saw gen-on-gen was 30% in the past 20 years. That was back in the glory days of scaling and when desktop CPUs were using less power than laptop CPUs do today. So they had room to grow.

2019: Clock speed wall, low hanging fruit picked for ILP, TDP wall, diminishing returns in process, increasing costs

They've got lot of work to do just to get 10% nowadays. More work, for less gains.

Again, look at how much Skylake had to change. Everything is relative. Back in 2017 it would have been acceptable. In 2020 that's a whole different story.

Not sure what your gripe with a 10 - 15% generational improvement is. What were you expecting beyond Skylake? A 30% boost? Let's party like its 1999?

A 10 - 15% IPC uplift would allow a 4.0 - 4.2GHz Sunny Cove to perform like a 9900K @ 4.7GHz - minus the heat and power consumption. 14nm power efficiency is optimal at the low 4GHz range, as seen by the '95W' 9900K @ 4.2GHz at GN. If 10nm has a similar efficiency curve relative to frequency (plus the power savings that come with a node shrink, lets say 25%) then we can expect 9900K performance at about 70W. Which then allows thermal / power headroom for higher core count chips to compete with next gen Ryzen, which is mooted to go up to 16 cores.

 

[Spartak]

Sure let's take the best-in-case synthetic performance increase (specint and probably not even C4C) and compare it against the geekbench results for an early icelake sample.

FYI Inteluser2000 the Geekbench score (which is more realistic BTW) for the A12 vs A11 is 9% clock for clock. For Icelake it's about 13-15% judging on the sample. And we don't know if sunny cove doesnt have tiger lake improvements so it might even be better. The least thing you could do is compare apples to apples but we all know that's too much to ask from you.

9% A12 vs 15% ICL is just 'slightly' different from 30% A12 vs 5% ICL.

But facts never stood in the way of people looking to troll.

 

[Phynaz]

Maybe.

Yikes.
That's a no from me chief.

I wonder why you think server customers care about how the CPU in their server was manufactured.

 

[Phynaz]

Not sure what your gripe with a 10 - 15% generational improvement is. What were you expecting beyond Skylake? A 30% boost? Let's party like its 1999?

A 10 - 15% IPC uplift would allow a 4.0 - 4.2GHz Sunny Cove to perform like a 9900K @ 4.7GHz - minus the heat and power consumption. 14nm power efficiency is optimal at the low 4GHz range, as seen by the '95W' 9900K @ 4.2GHz at GN. If 10nm has a similar efficiency curve relative to frequency (plus the power savings that come with a node shrink, lets say 25%) then we can expect 9900K performance at about 70W. Which then allows thermal / power headroom for higher core count chips to compete with next gen Ryzen, which is mooted to go up to 16 cores.

AMD gets a 10 - 15% uplift and people are hanging from the chandeliers. Intel gets a 10 - 15% uplift and they are doomed.

 

[Spartak]

AMD gets a 10 - 15% uplift and people are hanging from the chandeliers. Intel gets a 10 - 15% uplift and they are doomed.

Zen2 = second coming of Christ
Sunny Cove = Netburst revisited

Really looking forward to what AMD brings to the tables but cannot stand this fanboy cheering / dismissing

 

[Yotsugi]

I wonder why you think server customers care about how the CPU in their server was manufactured.

They sure af care about TCO, and Intel will need ~2 years at least to beat Rome in it.

AMD gets a 10 - 15% uplift and people are hanging from the chandeliers. Intel gets a 10 - 15% uplift and they are doomed.

2 years since Zen versus 4 (well actually 5) years since SKL.
I sure af expect Intel to bring MORE, like, pull something from TGL or anything.