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[Anandtech] Intel's Architecture Day 2018

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DrMrLordX

Lifer
Apr 27, 2000
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Many core turbo, not all.
Okay. I'll be surprised if they increase the "many core" turbo as well. Same uarch, same process . . .

Like I said, since it's an mobile only product it should be okay. I'll add that an unknown when it comes to Icelake is how the McIVR will affect the clocks.
Sunny Cove/IceLake on 10nm is "mobile only" in 2019, assuming Intel launches on time. That product is supposed to hit the desktop in 2020.
 

jpiniero

Diamond Member
Oct 1, 2010
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That would be odd.
What other options do they have? They would have to legitimately fix 10 nm to be able to really produce the volume. Like when I'm talking about Icelake Mobile, we're talking about maybe a couple mill of sales a quarter in 2020 when Intel sold 65M+ client processors last quarter.
 
Mar 10, 2006
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What other options do they have? They would have to legitimately fix 10 nm to be able to really produce the volume. Like when I'm talking about Icelake Mobile, we're talking about maybe a couple mill of sales a quarter in 2020 when Intel sold 65M+ client processors last quarter.
2020 is a ways from now.
 

DrMrLordX

Lifer
Apr 27, 2000
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All I can say is that, if Intel can't ship 10nm in volume by 2020, they're in for some trouble. Projecting a few million sales per quarter for IceLake Mobile puts it dangerously close to Cannonlake levels.
 
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jpiniero

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Oct 1, 2010
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All I can say is that, if Intel can't ship 10nm in volume by 2020, they're in for some trouble. Projecting a few million sales per quarter for IceLake Mobile puts it dangerously close to Cannonlake levels.
Cannonlake wasn't close to that. That was maybe a couple thousand, maybe in the tens of thousands. It's going to be weird, I'm sure.

2020 is a ways from now.
It can feel that way but it's only a few days until 2019...
 

witeken

Diamond Member
Dec 25, 2013
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I'm fully expecting the 2020 desktop to be 14 nm based.
I think after Comet Lake, the 2019 part, Intel is all in on 10nm and will ramp all the 10nm IP as fast as possible imo.

I mean, they should really be in a hurry given TSMC has already 7nm up and running, so I can't imagine them wanting to waste any more time stuck on 14nm and want to move on. But can they?
 

NostaSeronx

Diamond Member
Sep 18, 2011
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Amber Lake-Y Q3-Q4 2018 (24 EUs?)-> Icelake-Y Q3-Q4 2019 (64 EUs?) // 5W TDP
Coffee-U Q3-Q4 2018 (24 EUs?) -> Icelake-U(1st ver) Q3-Q4 2019 (64 EUs?) // 15W TDP
Comet-U Mid-2019 (24 EUs?) -> Icelake-R(2nd ver?) Early 2020 or Tigerlake-U Mid-2020 (64 EUs?) // 10W TDP?
Comet Lake-S Mid-2019 10-cores -> Icelake-S Mid-2020 16-cores?
Cooper Lake Mid-2019 28-cores -> Icelake Server(XCC) Mid-2020 44-cores?
=> Sapphire Rapids (XCC-effective) chiplet server 1.0 Mid-2021 (<80 willowcove cores) -> Granite Rapids (XCC-effective) chiplet server 2.0 Mid-2022 (>80 goldencove cores)

*shrug*
 

jpiniero

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Oct 1, 2010
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I mean, they should really be in a hurry given TSMC has already 7nm up and running, so I can't imagine them wanting to waste any more time stuck on 14nm and want to move on. But can they?
Yeah that's the thing. I don't think Intel will actually fix 10 nm. With small dies and some creative binning you can still deliver some product though.
 

NostaSeronx

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Sep 18, 2011
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Sapphire Rapids is Willow Cove?
Willowcove* or WLC

It could be Sunnycove-X(Server core or Super core vs Sunnycove as a Big core) for all that it is worth, but that would mean CMT;
3 ALUs + 2 512b FMACs * 2
with each getting 1 LD/1 STA/1 STD in balanced mode or 2 LD/2 STA/2 STD in competitive mode.

Since, Intel has failed to disclose their ultra-wide CMT cores as of yet. I'll shrug it off.
 

NTMBK

Diamond Member
Nov 14, 2011
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Willowcove* or WLC

It could be Sunnycove-X(Server core or Super core vs Sunnycove as a Big core) for all that it is worth, but that would mean CMT;
3 ALUs + 2 512b FMACs * 2
with each getting 1 LD/1 STA/1 STD in balanced mode or 2 LD/2 STA/2 STD in competitive mode.

Since, Intel has failed to disclose their ultra-wide CMT cores as of yet. I'll shrug it off.
That's probably because CMT is awful, and Intel have no intention of using it.
 
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NostaSeronx

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Sep 18, 2011
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That's probably because CMT is awful, and Intel have no intention of using it.
That is your opinion, but the industry has stated otherwise. If a custom core DSP/x86/RISC architect wants more IPC, the natural path is CMT to CSMT. Of which Intel is guaranteed to implement in some form because of Bulldozer/Piledriver/Steamroller/Excavator designers and the whole of SoftMachines employees. There is also the Itanium/x86 SW-HW project that was before those acquisitions, which explored CMT in Itanium w/ Super-EPIC; Super-word execution which was superscalar-esque. Which all of these projects fell into the Cove lineage of cores. To max out the deepness, wideness, smartness, etc...

The cores are going to get bigger and Intel is going to use every technique in the book. To make them as big as possible and to max out IPC in every way. Every way being... the architecture via OoO and beyond or the compiler via AutoVectorization or programmer by hand. No way of optimization is going to be left behind.
 
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Spartak

Senior member
Jul 4, 2015
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Exactly! So accusing others of believing the earth is flat because there are "facts" that prove them wrong when there are none is just amusingly ridiculous :)
Someone is making a claim when there is enough information available to know that claim is not realistic. Furthermore there are geekbench benchmarks that point to the same conclusion.

We'd be safe to assume posters here know a thing or two about microprocessor design. Spreading falsehoods while claiming to be on the side of 'facts' is simply a hypocritical stance to take, hence my reference to FES.

Nothing is ridiculous but the original post I responded to.
 

Markfw

CPU Moderator, VC&G Moderator, Elite Member
Super Moderator
May 16, 2002
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Someone is making a claim when there is enough information available to know that claim is not realistic. Furthermore there are geekbench benchmarks that point to the same conclusion.

We'd be safe to assume posters here know a thing or two about microprocessor design. Spreading falsehoods while claiming to be on the side of 'facts' is simply a hypocritical stance to take, hence my reference to FES.

Nothing is ridiculous but the original post I responded to.
Opinions here are allowed, and all over the board, but until there is a product, with reviews, all of it is still opinion. Including links to what Intel alludes that they will be doing. Its still their opinion, until a product is out. I am not taking sides here, just that Intel has a bad track record as of late, so I don't trust what they say, only what product I see.
 

Spartak

Senior member
Jul 4, 2015
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An Fmax drop of 10% combined with an IPC gain of 11% = standing still. That's the problem; you don't upgrade just to stand still. It's why Ryzen hasn't been widely accepted as an upgrade from say a 2500/2600K.
I suspect that the ne t gen Ryzen will become the pinnacle for some time, though it won't be much better than the 9900K itself.
Whilst it is great to have choice at the top end, it's just a shame that the performance gains from one generation to the next are so anaemic.
that's why we will see sunny cove on 14nm. some people here think roadmaps from a year ago are set in stone when we just had a whole briefing showing they turned their original plans upside down.

pretty easy to dismiss something when intel themselves have already stated between the lines we wont see desktop on 10nm for precisely that reason. the desktop will move from 14 to 10nm+, where fmax is as good or better.

stating desktop will move to first gen 10nm is beating a dead horse nobody but you and some other flat earthers are still beating.
 
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coercitiv

Diamond Member
Jan 24, 2014
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The poor attempts at sarcasm in this thread are getting awfully close to insults, and they also seem to prevent some users from discerning basic semiconductor facts. The irony has come full circle.

Sunny Cove, even if it achieved it's perf. / clock goals, will use inherently more power to run at iso clocks (efficiency may hopefully go up, but absolute power will definitely go up). Couple that with 9900K being already very power constrained, and it should be immediately obvious that both base clocks and sustainable all-core boost clocks are bound to come down. So even by staying on 14nm the new design will lose clocks. (except for the single-core marketing figure, that can stay nice and pretty - and mostly useless)

Delivering desktop Sunny Cove on 14nm is just as big of a compromise as it would be on their unrefined 10nm, it will affect high core count throughput just as badly, if not worse (some say 10nm fmax drop would be horrendous, I dissagree but respect their estimate, it is possible). The only undisputed advantage 14nm has over 10nm is yields. And what an advantage that is, unless Intel finally managed to work magic on 10nm.

The only piece of great news I see in Intel entertaining 14nm Sunny Cove is the resulting performance related conclusion - in order for a significantly bigger core to be considered better on the same process, the new design must be clearly more efficient, since it must overcome both extra power and transistor cost. If it only made sense on 10nm then we could have still argued the gains are only marginally compensating the costs. Not on 14nm though, it needs to pull it's full weight on the older process.

That having been said, Happy New Year! 2019 looks life fun times on the CPU front.
 
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DrMrLordX

Lifer
Apr 27, 2000
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That is your opinion, but the industry has stated otherwise.
Still stumping for CMT, are we? Some things never change.

It should be Golden Cove.
I am more inclined to believe that than . . . you know. Consider the source.

That having been said, Happy New Year! 2019 looks life fun times on the CPU front.
Indeed. Might not be so much fun for Intel, though. We'll see. Maybe they'll turn it around.
 

naukkis

Senior member
Jun 5, 2002
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Still stumping for CMT, are we? Some things never change.
Against side-channel attacks only reliable solution is to separate L1d from each other. Intel Sunny Cove seems to have totally doubled L1-data access and one reason to for it is to split L1-accesses totally to each thread when running multiple threads. To continue at that path next logical step is to isolate L1i also from other thread. What AMD solutions did not have was possibility to use all resources from two threads when running single thread - with that CMT is the right way to do SMT and maintain privacy between threads.
 

naukkis

Senior member
Jun 5, 2002
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The L1d increase is 50%.
I mean data access, Sunny cove will have double everything, agu's, store ports etc. to be able to split data access exclusively per thread with two threads. L1d size is not a matter and could still be dynamically split between threads.
 

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