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News [Anand] Intel's Enterprise Extravaganza, Cascade Lake Launches

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LTC8K6 said:
Apparently no one read it the first time it was posted...
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I knew it far back as when this came out: https://3s81si1s5ygj3mzby34dq6qf-wp...loads/2018/07/intel-hpc-roadmap-june-2018.jpg

It was even on Anandtech's news page. But tech sites are for consumer enthusiasts. You don't know about trucks just because you know about fast cars.

Cooper Lake-SP uses the same platform as Ice Lake -SP so it'll use the LGA 4189 socket. Making it socketable increases motherboard size and complexity, hence BGA for Cascade Lake -AP. You'll see the motherboard for -AP is quite small.

I think the criticisms against Intel are valid, but people are misunderstanding the -AP line.
 
Markfw said:
And EPYC with 64 cores is not as dense ?
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Not necessarily, no. If you need/want AVX-512 then Rome is simply not an option.

SarahKerrigan said:
Epyc with 64 cores doesn't presently exist.
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Really? I'm pretty sure someone has at least samples, if not early commercial chips of 64c Rome right now. You can't buy them from a system integrator or anything, but if you're Google/Amazon/etc. then yeah, they've probably got them.

Zucker2k said:
Has AMD even implemented AVX-512 in Rome?
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Either a). no or b). not in any meaningful way. It would be like running 256-bit AVX2 on EPYC, perhaps worse.

IntelUser2000 said:
I think the criticisms against Intel are valid, but people are misunderstanding the -AP line.
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Yarr too true.

-AP = Phi replacement
-SP = "actual" Xeons

Rome's competition in the short term is Cascade Lake-SP, and later Cooper Lake-SP. Nobody would buy Cascade Lake-AP for a cloud server, just as they wouldn't buy Cascade Lake-SP for HPC number crunching.
 
IntelUser2000 said:
Nah, its been known as Cascade Lake-X for a long time. The HEDT parts always have a quarter or so delay from the server parts. Since -SP was introduced just now, expect the -X parts around summer.
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Yeah, I was reading a bogus article. I finally found an updated server roadmap (no dates):

arch-day-2018-sailesh-roadmap.png
 
DrMrLordX said:
If you need/want AVX-512 then Rome is simply not an option.
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Do we already know if/how much of AVX-512 Zen 2 will/won't support? If Zen 2 does handle AVX-512 similarly to how Zen 1 did AVX2 I don't think the answer is as clear cut as you put it.
 
moinmoin said:
Do we already know if/how much of AVX-512 Zen 2 will/won't support? If Zen 2 does handle AVX-512 similarly to how Zen 1 did AVX2 I don't think the answer is as clear cut as you put it.
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Zen2 gets a major update for AVX over Zen1.


In Zen, AVX2 256 bit single and double precision vector floating-point data types were supported through the use of two 128 bit micro-ops per instruction. Likewise, the floating-point load and store operations were 128 bits wide.
In Zen 2, the datapath and the execution units were widened to 256 bits, doubling the vector throughput of the core.

With two 256-bit FMAs, Zen 2 is capable of 16 FLOPs/cycle.
 
Jimzz said:
Zen2 gets a major update for AVX over Zen1.


In Zen, AVX2 256 bit single and double precision vector floating-point data types were supported through the use of two 128 bit micro-ops per instruction. Likewise, the floating-point load and store operations were 128 bits wide.
In Zen 2, the datapath and the execution units were widened to 256 bits, doubling the vector throughput of the core.

With two 256-bit FMAs, Zen 2 is capable of 16 FLOPs/cycle.
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Exactly. And with Zen 1 the two 128-bit (AVX) FMAs could be combined to one 256-bit (AVX2) operation. The question is whether Zen 2 allows combining two 256-bit (AVX2) FMAs to offer one 512-bit (AVX-512) operation or if the AVX-512 instruction set is still completely unsupported.
 
moinmoin said:
The question is whether Zen 2 allows combining two 256-bit (AVX2) FMAs to offer one 512-bit (AVX-512) operation or if the AVX-512 instruction set is still completely unsupported.
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Right now we have no indication that AVX-512 is supported at all. It's possible that they support only AVX-512F. We just don't know. The main thing to remember is that Intel had to completely re-engineer elements of the Skylake core when creating Skylake-SP (changes that persist in Cascade Lake) to accommodate AVX-512. Simply fusing two FMACs in an attempt to handle 512-bit SIMD may not be . . . eh I dunno.

It just seems to me that the departure from AVX2 to AVX-512 was sufficiently radical that there's more to it than just widening/doubling everything.
 
moinmoin said:
Exactly. And with Zen 1 the two 128-bit (AVX) FMAs could be combined to one 256-bit (AVX2) operation. The question is whether Zen 2 allows combining two 256-bit (AVX2) FMAs to offer one 512-bit (AVX-512) operation or if the AVX-512 instruction set is still completely unsupported.
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I'm 90% sure AVX-512 is not supported in any form on Zen 2. The reasoning:

1) AVX-512 instruction-set is not just a 2x wider AVX-2. It actually has new unique instructions. These also have 256 and 128 bit wide versions, which don't have analogs in AVX or AVX2. So it's not that easy to support via micro-code only, unless AMD has already implemented a subset of AVX-512 with vectors <= 256 bit. We will probably have to wait until at least Milan, to get that support
2) In the TACC Supercomputer article (that ended up using Cascade Lake) they specifically mentioned that they would need to change the client code for Rome (compared to Skylake-X). That would not be necessary, if it supported AVX-512 via multiple micro-ops

EDIT:
Damn DrMrLordX beat me to it 😀
 
Gideon said:
Damn DrMrLordX beat me to it 😀
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I hadn't read didn't remember (oops I did read that, months ago!) that TACC Supercomputer article, and it does give us a pretty good hint as to whether Rome would support the full AVX-512 suite (it probably doesn't). So you got me there.
 
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