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Question 'Ampere'/Next-gen gaming uarch speculation thread

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Ottonomous

Senior member
How much is the Samsung 7nm EUV process expected to provide in terms of gains?
How will the RTX components be scaled/developed?
Any major architectural enhancements expected?
Will VRAM be bumped to 16/12/12 for the top three?
Will there be further fragmentation in the lineup? (Keeping turing at cheaper prices, while offering 'beefed up RTX' options at the top?)
Will the top card be capable of >4K60, at least 90?
Would Nvidia ever consider an HBM implementation in the gaming lineup?
Will Nvidia introduce new proprietary technologies again?

Sorry if imprudent/uncalled for, just interested in the forum member's thoughts.
 
To lose money on <400 dies and a price tag of a card of $400 would mean that nobody could produce any consumer GPU on TSMC's 7nm process...

What you said is since they're producing 827mmq dice they can't be less concerned about money.

Those dice are sold at such a premium they are no indication about how much nvidia is willing to spend money.
 
What you said is since they're producing 827mmq dice they can't be less concerned about money.

Those dice are sold at such a premium they are no indication about how much nvidia is willing to spend money.
This. A GV100 based AIB is about $9K US. I'm sure GA100 is even more, and is currently only available in a mezzanine form factor (actually, only as a system right now, IIRC).
 
The "Ampere" A100 Whitepaper:

https://www.nvidia.com/content/dam/...ter/nvidia-ampere-architecture-whitepaper.pdf

That's a rather dramatic improvement in TC performance, it will be interesting to see what they end up looking like in the consumer GPUs down the line.
From a quick read-through, there doesn't appear to be big changes to the non-TC portion of the SM beyond an increase in cache size and async copy/barriers, which would help improve the raw IPC. On the gamer side of the Ampere GPUs, I think the rumors of a modest increase in raster performance but significantly improved RTRT and DLSS are going to be true: they will revamp the RT units and use the heavily-beefed up TCs for faster denoising.
 
The die may be very large, but that is more than made up by the high selling costs. Same with server CPUs. 600mm2+ CPUs exist on server because they sell for thousands of dollars. Much better profit margin compared to selling a 100mm2 for $100.

Considering how useful DLSS 2.0 seems to be I have to say Ampere's perceived lack of FP32 increases doesn't seem that bad. With touted RT and Tensor core changes, it might just make ray tracing truly viable.
 
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This is a bit off topic, but I love that everybody commenting on a phone/tablet is getting "dies" replaced with "dice". It just totally changes the whole connotation of the comment 🙂
 
This is a bit off topic, but I love that everybody commenting on a phone/tablet is getting "dies" replaced with "dice". It just totally changes the whole connotation of the comment 🙂

I'm actually typing dice, but this is not my native language, am I wrong?
 
I'm actually typing dice, but this is not my native language, am I wrong?
Not wrong, english is just fun. Die, dies and dice would all be functional for the plural form of die. I can say from a manufacturing point of view that wafers are diced (cut) into an individual die.
 
I'm actually typing dice, but this is not my native language, am I wrong?

Ahh, ok. This explains it, sorry for making light of it. "Dice" are what you role roll during many types of games. Such as below:
1589980772280.png

For things like CPU's or GPU's, its "Die" for singular, or "Dies" for plural.
 
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Just because its amusing in context 🙂 Roll not role in Stuka's post above.

Die is used in a number of contexts. Silicon dies are presumably from die casting etc in metal working. I've no idea why the singular of dice is the same word.

English is often deeply baffling.
 
Okay, so what about the official statement that TSMC would be producing the bulk of NV GPUs?
They said specifically, that bulk of 7 NM GPUs will be manufactured on TSMC process.


Not that ALL of their next gen GPUs will be manufactured at TSMC's 7 nm process.
 
They said specifically, that bulk of 7 NM GPUs will be manufactured on TSMC process.


Not that ALL of their next gen GPUs will be manufactured at TSMC's 7 nm process.
Yeah, there is some wiggle room there. Unfortunately, it seems that no one (who actually knows) is spilling the beans.
 
So its not going be as efficient as everybody hopes?

Who would have thought that? 😉
Maybe not. Doubt it's an error by NV (well, wrt to shader cores - don't know about RT or TC). I'm inclined to think, if this is true, that GA102 is a monster and or clocked through the roof.
 
Maybe not. Doubt it's an error by NV (well, wrt to shader cores - don't know about RT or TC). I'm inclined to think, if this is true, that GA102 is a monster and or clocked through the roof.
Or simply on smaller nodes any efficiency gains are going out the window at the expense of higher clock speeds.

Look at GA100 chip. Its 400W GPU with HBM2 and on 7 nm TSMC node, which is better than Samsung's 8 nm LPP. And its clocked "only" at 1.4 - 1.5 GHz. Without specific physical design optimizations, similar to Volta/Turing we should not expect any ground breaking efficiency on smaller nodes.

Don't be surprised if RTX 2080 Ti replacement will consume 300W of power. Similar thing will happen to Intel and AMD if they will go for larger die sizes.
 
Maybe not. Doubt it's an error by NV (well, wrt to shader cores - don't know about RT or TC). I'm inclined to think, if this is true, that GA102 is a monster and or clocked through the roof.

I'm sure that performance/watt will be very nice but overall consumption could be high.
 
Don't be surprised if RTX 2080 Ti replacement will consume 300W of power. Similar thing will happen to Intel and AMD if they will go for larger die sizes.
I'm sure that performance/watt will be very nice but overall consumption could be high.

Yeah, 300W makes much more sense to me than 375W. I think the 3080Ti and Big Navi will be monsters (for ASICs).
 
well, 375W is simply the power draw combined from two 8 pin connectors, and PCIe lanes. I never expected that next gen will run around 375W of power, but fully expected it will be consuming more power than previous gen. 300W fits perfectly the reality we are facing on smaller nodes, and what could be witnessed on both: RDNA1 and Ampere.
 
Also Im surprised nobody is bringing up the second info Kopite today wrote.

GDDR6X for Next gen Gaming cards, with more than 20 Gbps?
 
well, 375W is simply the power draw combined from two 8 pin connectors, and PCIe lanes. I never expected that next gen will run around 375W of power, but fully expected it will be consuming more power than previous gen. 300W fits perfectly the reality we are facing on smaller nodes, and what could be witnessed on both: RDNA1 and Ampere.
Oh, LOL!
Also Im surprised nobody is bringing up the second info Kopite today wrote.

GDDR6X for Next gen Gaming cards, with more than 20 Gbps?
Well, if true, that makes some of the speculation about really wide memory buses for the consumer Ampere lineup pretty silly. GDDR memory has been moving along at an impressive pace IMHO.
 
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