AMD's "Thorton"... What's the point?

[Ilmater]

I believe this is more about AMD than a specific CPU, so I posted it in General, but mods, feel free to smack me down if neccessary.

I just read this article, and at the bottom it mentions that speculation about the Thorton. They say the Thorton is the Barton with TBred cache. Why is this even mentioned? Who are the hardware enthusiasts that are speculating about this? I'm not sure what architectural differences there are between the Barton and the Thoroughbred, but there aren't that many other than the cache, are there?

Usually, rumor is at least interesting. This seems worthless to me. Am I missing something? Should I be interested in this?

 

[BD231]

I thought I rember hearing it had better thermal something......., I can't imagine they did much of anything else when you consider the poor performance gain the Barton got over the T-Bred.

 

[AtomicAlien]

Why bother then? What arcitecture enhances does the Barton have that it should have a "celery" equivalent. It would basicall be a Tbred then...

 

[Elcs]

I believe Barton introduced some form of CPU throttling. I think the Barton shuts down parts of itself to stop it overheating much like the P4. However, I read that if every single CPU cycle is being used, then this throttling doesnt work. This is the only improvement I can see the Thorton having over the T'Bred, unless they are going to release higher speed chips or even work on the 400 fsb.

 

[Lord Evermore]

Easier to have only two production lines, producing nearly the exact same core with only the cache different? Rather than continuing production on t-bred and having to make new revisions to both cores? I don't know how much longer they'd actually continue producing t-bred cores of course, so maybe this just adds one more line now but will result in a reduction later.

Or maybe they've just got stacks and stacks of Barton's that didn't have fully working cache.

This makes it seem like it's not really a Barton core though... http://pc.watch.impress.co.jp/docs/2003/0318/kaigai01.jpg

 

[Jhhnn]

The one thing it would accomplish is that AMD could recover and sell some barton cores that might otherwise become scrap, much as the 128K cache celerons came from p2 cores, although that may not be an issue any more. It would allow AMD to phase out separate production of Tbreds as they move into their newer architectures...

 

[Jeff7181]

A Barton with a T-Bred cache is a T-Bred... the only difference between the Barton and the T-Bred is the amount of L2 cache.

 

[Ilmater]

Originally posted by: Jeff7181
A Barton with a T-Bred cache is a T-Bred... the only difference between the Barton and the T-Bred is the amount of L2 cache.

If that's true (and I don't doubt that it is), then why the bother even talking about a Thorton? Why would AMD deny it if it's such a useless idea?

 

[Remedy]

OT: Barton feature "S2K". Tbed doesn't. So Thorton feature this.

 

[Lord Evermore]

?

 

[Remedy]

Lord. S2K

My point is, Barton features Signal to bus disconnect. Tbred doesn't. If Thorton is based off of Barton core, then yes it has a feature that Tbred doesn't. Making it brother of Barton and not Tbred.

 

[MadRat]

Here's the gist:

Moreover, with the launch of the new Barton based processors, AMD decided to start setting mainboard guys on the right track. A while ago AMD forced the mainboard manufacturers to implement a special CPU thermal protection scheme using the integrated thermal diode. If this hadn't been done, the mainboard wouldn't have been certified by AMD. As we see, the results are evident: most mainboards available in the today's market do have a CPU thermal protection scheme.

The second move on AMD's way had to do not with the CPU protection against burning, but with the temperature reduction during work. Now AMD Company will require all mainboards applying for certification to support S2K Bus Disconnect function, which will allow reducing the average consumed power and the heat dissipation of the CPU in most Windows applications without any performance losses. The S2K Bus Disconnect implementation implies the following. During HALT command (HALT means the CPU will be stopped because there are no instructions to be processed), the CPU can be switched to the corresponding waiting mode (Halt and Stop Grant) with lower power consumption and heat dissipation. However, Athlon XP also required System Bus Disconnect to be able to switch to the lower power consumption state. In fact, this should be implemented in the mainboard chipset and BIOS. But until recently, the BIOS of most mainboards used to be configured in such a way that Athlon XP never got to the lower power consumption state. As a result, even in idle mode the temperature of all Athlon XP processors remained pretty high.

Now the situation should change drastically and Athlon XP processors will become much cooler on those mainboards, which will support S2K Bus Disconnect. Many today's chipsets, such as VIA KT400, VIA KM400, SiS 746 and NVIDIA nForce2 do support S2K Bus Disconnect without any problems. There have already appeared the first mainboards, where the Bus Disconnect feature may be enabled in the BIOS. So far there are only five mainboards like that. They are: ASUS A7V8X v1.04, EPoX EP-8K9A2, Gigabyte GA-7VAXP v1.0, Gigabyte GA-7VAX v1.1 and Gigabyte GA-7VA v1.0. However, since they do not certify any more mainboards without the support of Bus Disconnect function, this list should very soon grow longer.

 

[sirfergy]

The P4 already does something like that right?

 

[mechBgon]

Originally posted by: sirfergy
The P4 already does something like that right?

Yep, here's a good article that covers the P4's setup nicely: article

 

[Wingznut]

Originally posted by: Lord Evermore
Or maybe they've just got stacks and stacks of Barton's that didn't have fully working cache.

This is actually a very good point, that doesn't appear anybody has picked up on.

During manufacturing, if you get a defect in the cache, often times you can turn off sections of the cache, and the chip will still be functional... Just not have all of the cache available.

By offering another product line, AMD saves themselves from just throwing this silicon away.

 

[Lord Evermore]

You edited the post, so I'm assuming I wasn't seeing things and it originally said B2K like I thought. I couldn't figure out if you were being sarcastic about ads featuring the music group or what.

As for S2K, it isn't that Barton supports S2K while T-bred didn't, but merely that AMD is now requiring that motherboard BIOSes implement it in order to be certified for supporting Barton. S2K is as much a function of the motherboard as the CPU, and most or all recent chipsets have supported it. Athlon has always supported it, even the K6 series did I think, though I don't think it was named S2K back then. That's all that programs such as CPUIdle and Rain did, issued HALT commands, and Unix/Linux do it natively, as does the ACPI configuration of Windows.

 

[Remedy]

I stand corrected again. Another day of defeat. Thank the Lord.

 

[Ilmater]

Originally posted by: Wingznut

Originally posted by: Lord Evermore
Or maybe they've just got stacks and stacks of Barton's that didn't have fully working cache.

This is actually a very good point, that doesn't appear anybody has picked up on.

During manufacturing, if you get a defect in the cache, often times you can turn off sections of the cache, and the chip will still be functional... Just not have all of the cache available.

By offering another product line, AMD saves themselves from just throwing this silicon away.

But why is there a new "name" for them and why is AMD denying it? It doesn't make sense. Unless there's actually a difference (which so far I haven't heard of), then why is there a "code name" for it and why is it anything worth even talking about?

 

[BD231]

Originally posted by: Ilmater

Originally posted by: Wingznut

Originally posted by: Lord Evermore
Or maybe they've just got stacks and stacks of Barton's that didn't have fully working cache.

This is actually a very good point, that doesn't appear anybody has picked up on.

During manufacturing, if you get a defect in the cache, often times you can turn off sections of the cache, and the chip will still be functional... Just not have all of the cache available.

By offering another product line, AMD saves themselves from just throwing this silicon away.

But why is there a new "name" for them and why is AMD denying it? It doesn't make sense. Unless there's actually a difference (which so far I haven't heard of), then why is there a "code name" for it and why is it anything worth even talking about?

They're dumb.

 

[Wingznut]

Originally posted by: Ilmater
But why is there a new "name" for them and why is AMD denying it? It doesn't make sense. Unless there's actually a difference (which so far I haven't heard of), then why is there a "code name" for it and why is it anything worth even talking about?

First off, just because theinquirer talks about it, doesn't make it so. Take those words of advice, and embrace them.

I have no idea if there are plans for such a product... I'm just saying that (in my humble opinion, of course) it would be reasonable if AMD were to travel down that road.

AMD may not want to discuss future products that aren't finalized, because it would in no way benefit them. Or maybe there is no such product in the works.

 

[bgeh]

this may be pure speculation, but this was what i found when i was searching for an update for my Abit NF7-S bios
Link

1.Please use AWDFLASH 8.23D or later to update NF7 series BIOS. With
incorrect AWDFLASH version, the GUID will be erased, and leads to
IEEE1394 peer to peer function failed. AWDFLASH 8.23D is included in
this BIOS package.
2.Change the write-protection mechanism of Flash ROM programming.
3.Support Thorton, Throughbred, Barton 2600+ CPU.
4.The default value on DRAM Ration changes to"Auto".
5.Added "CPU Disconnect Function" option on chipset to turn on/off C1 disconnect.
6.The CPU frequency 1917Mhz revised to 1916MHz.
7.DMI Pool data shows to"socket A".
8.The default value of "Memory Timings" revises to "Optimal".
9.Fix the problem that system can not detect USB Device under WinME while resume from S3,S4 mode, and lead to usb connector failed.
10.Fix system can not show fan speed in PC Health Status while using lower
speed FAN.
11.Add"IDE Bus Master" function to improve transfer speed of GHOST, and
default value set up to disabled.
12.Fix the problem while disabled"IDE Controller", and truned off IDE Controller, it would fail to share IRQ 14, 15;thus, IDE Controller would NOT be turned off, it would show "IDE Controller"IRQ to be "NA" in PCI list.
13.Provides"AGP aperture size" option for NF7-M, while use on chip VGA.
14.BIOS compile date: 3/27/2003.

 

[MadRat]

Just makes sense that Thornton replaces Duron.

 

[Whitedog]

None of the new P4's are being made with 256k cache are they? (I know, celery, but that doesn't count here) I don't think so... SO WHY THE FARFINUGLE is AMD still putting 256k cache in them? The Dolts! WHy don't they just call the 256k chips Durons.

They've already came out with the 512k chips, so they need to just abandon the idea the 256k L2 is acceptable!

DOWN WITH 256k!!!!!

 

[Lord Evermore]

Duron is only a 64k L2 cache. So a 256k CPU is still way better. If it makes sense for Intel to be making 512K P4s and 128K Celerons, why doesn't it make sense for AMD to be making two cache levels? Duron is already dead.

 

[MadRat]

256k cache could be meant as 128k L1 + 128k L2.

I'd like to see AMD up the ante and increase their baseline L1 to 256k. This way the consumer Hammer (aka Athlon 64) could be a no-L2 cache CPU and then commercial versions would support the 512K or 1M L2 caches. I'd like to see Athlon 64 just stick to the Opteron socket, too, so its allows us to upgrade from the consumer chips to the commercial grades. This way the consumer-version Hammers could be fielded in anywhere from 1-8 CPU arrays but in no way would they endanger the Opteron market.