Originally Posted by hardware.fr by google translate
AMD shows first of all that the heart of the architecture has been improved for better energy efficiency. As NVIDIA has begun to do from the Kepler generation, we can assume that AMD will try not need a complex logic and greedy scheduling within the CU, where the behavior of After a certain statement is fully deterministic and can therefore be satisfied with a static schedule prepared at compile time. AMD is also talk of improved hardware schedulers, but this time we assume they do not refer to CU but front-end and global tasks initiated by the control processors. It is thus probably enhancements designed to support multi-engine Direct3D 12. There is also talk of new compression modes. It could be the ASTC compression, costly to implement (but this problem 14nm rule) and AMD and Nvidia had avoided so far, unlike the GPU SoC designers to where a few more transistors are never too expensive paid to save memory bandwidth and energy. Finally, AMD mentions a Primitive Discard Accelerator or an ejection system triangles masked the rendering pipeline. Remember, statistically, about half of the triangles of an object turning their backs to the camera and may be ejected from the rendering soon as this state is confirmed. Able to quickly make geometry can boost performance in real situations. Currently, the Radeon geometry engines are not able to perform this task faster than rendering a triangle, unlike GeForce who benefit to stand out in some scenes, especially when tessellation generates many hidden triangles. With Polaris, AMD should finally fill the gap, probably doubling the number of ejection motor engines primitive rasterization (Nvidia opted for a different approach by decentralizing some of the geometry processing but we do not expect that AMD follows this route).