Discussion AMD's Future CPU-APU (Prometheus!?) Gone ARM !!!

[Tigerick]

7. Zen 7 no more - Prometheus is AMD's first custom ARM core after Soundwave.

Lisa Su says AMD is on track to a 100x power efficiency improvement by 2027.

 

[Cheesecake16]

7. Zen 7 no more - Prometheus is AMD's first custom ARM core, period.

Tell me you haven't heard of AMD K12 without telling me you haven't heard of AMD K12...
That was AMD's first custom ARM core and it went nowhere...

And no, AMD won't abandon x86... that is a silly train of thought... there is far too much money in the x86 market that will never go away...

 

[Gideon]

And no, AMD won't abandon x86... that is a silly train of thought... there is far too much money in the x86 market that will never go away...

They don't have to abandon them outright. In 10 years a Legacy business software can easily be catered to with incremental updates to legacy cores. They migh t sill focus to other ISAs.

I do agree though that they will only go that way if they must. competing in the ARM or RISC-V market will definitely be more challenging than competing with Intel, so AMD will want to avoid it as long as possible.

But if Nvidias ARM SoC's gain any traction (20+% market share) within the traditional desktop/laptop market, AMD might be more interested in dabbling with other ISAs as well.

 

[StefanR5R]

Mike Clark mentioned above statement regarding performance per watt. For comparison, I have created a table comparing x86 and ARM with GeekBench 6 ST performance, and I hope nobody believe what Mike claimed about PPW.

First, M. Clark spoke about AMD-x86 vs. AMD-ARM when he mentioned "same performance per Watt".
Second, if interested in performance per Watt of different CPUs in Geekbench, how about running n instances of Geekbench ST (n = number of hardware threads), measure task duration and task energy [EDIT: at the processor socket or/and at the computer PSU], then calculate performance per Watt.

Qualcomm, Mediatek not to mention Apple's M4 are all surpassing AMD's KRK/STX in single thread performance with fanless design.

Fanless designs are not very common in the datacenter; they are common in handsets.

 

[StefanR5R]

Have you wonder how Microsoft going to support upcoming ARM vendors like NV, AMD, Mediatek and Samsung? Microsoft could hard patch the OS to allow all upcoming CPU vendors to access low level kernel; Or Microsoft could launch brand new OS like Windows 12 ARM supporting all CPU vendors ?

According to Wiki, MacOS 15 has been updated to support ARMv9 in the operating system level. Microsoft could follow steps to modermize OS by supporting ARMv9 as well.

Firmware standards and device drivers are much more relevant in the question of porting an operating system to a platform; CPU ISA version not so much.

 

[soresu]

Claims in scientific papers have to be impressive

The baseline is clearly defined by a named open source RISC-V out or order CPU core design to compare against, so it's not like they are just pulling numbers out of thin air even if they are simulated or FPGA.

 

[Doug S]

3. The Arrival of LPDDR6

LPDDR6 will bring huge bump in memory bandwidth, that's mean all vendors will bump the core counts of CPU, GPU and NPU. With more cores, so does the power consumption. x86 with high clock speed won't be able to scale without big bump in power usage. There was rumor about Qualcomm's next gen X-Elite with 192-bit memory bus comes with 18 cores. And if my speculation is correct, upcoming Apple M5 Pro with 192-bit LPDDR6 should get bump of 14-core to 18-core as well ? We are talking about monolithics SoC, not chiplet design which is more expensive and power hungry..

You're way too impressed with LPDDR6 from a memory bandwidth standpoint. Keeping the number of bits constant (i.e. comparing 96 bits of LPDDR6 with 96 bits of LPDDR5X) I doubt the first gen LPDDR6 is going to offer much of a bump over LPDDR5X, let alone its non standard cousin LPDDR5T. It has room for growth but that's always the case that when they iterate a standard whether LPDDR, DDR, PCIe, TB or whatever that they make sure they provide a roadmap for increased speeds, typically double (though that's not reached until several years in for memory standards that don't do 2x jumps all at once like bus standards)

Anyway, OEMs are hardly holding back on core counts due to lack of memory bandwidth. Few applications are limited by current levels of memory bandwidth, especially for CPU. Sure you can come up with some benchmarks and a few applications that would make hefty gains if you doubled their available memory bandwidth, but most stuff wouldn't see any improvement at all. I don't know enough about the gaming world to say whether there are a lot of titles that max out current iGPU bandwidth - and have it matter rather than people simply opting to buy a dGPU to resolve that issue - but I'd be surprised.

AI certainly stands to benefit from increased memory bandwidth, but we'll have to wait and see if there is any real benefit to consumers from having an AI so powerful that the current ~ 75GB/sec or so in phones is seriously limiting them. Marketers will market, but whether that drives product design decisions a few years from now is another matter.

 

[Tigerick]

9. Venice 192-core (600W) -> Vera Superchip 176-core (100W) -> Prometheus



While I am trying to create a table listing potential Vera specs, Bionics and HXL has pretty much confirmed about Venice SP7/SP8 specs and TDP. Thanks to the leaks, I have pretty good idea about Venice platform which seems confusing at first. Let's go point to point:

• First of all, there are 2 Zen6 dies: Zen6 with 12-core and 48MB L3 cache will be fabbed by N3P process, not N2 as last rumor leaked. Zen6c with 32-core and 128MB die will be fabbed by N2 process. Two Zen6 will be used for next gen client CPU; that make total 24 max core counts.
• By doubling the L3 cache, Zen6c and Zen6 should share most of the features.....except clock speed due to extra 20 cores in Zen6c. More on that later.
• SP7 platform will support 16-channel DDR5. So far there is one model leaked with 8 Zen6c die and 2 IOD. Each IOD should support 8-channel DDR thus SP7 requires 2 IODs.
• SP8 platform will support 8-channel DDR5. By cutting half of memory bandwidth, SP8 could only support up to 128 Zen6c / 96 Zen6. Yep, it is lower than Turin Dense with 12-channel memory bus.
• Here comes my understanding of TDP numbers. According to leaks, 256-core should come with 600W, each Zen6c should consume 50W and each IOD should consume 100W. That sum up total 600W.
• 96-core Zen6 with 400W: Each Zen6 should consume 40W and IOD should consume 80W (without linking to other IOD). Total 400W.
• 128-core Zen6c with 350W: After deducting 80W IOD power, each Zen6c die should consume 67.5W which is higher than Zen6c in SP7. My thinking is AMD might try to clock Zen6c higher so that the difference between 96-core Zen6 and 128-Zen6c will be as small as possible. Thus, AMD could command higher price tag for 128-core.
• 192-core Zen6c with 600W: Bionic believe Zen6 die will be used in SP7 platform. I don't think so, there is no point putting more than 8 dies in SP7 when Zen6c is able to fit in the core counts. What we are lacking is HP Zen6c: And if we apply 67.5W with 6 dies, we get total sum of 605W. Thus, I believe AMD will use 6 Zen6c die to create high performance 192-core...

 

[branch_suggestion]

Is AMD really that hard to understand?
Creating a biased argument by omission and outright misinterpretation to this degree is actually making my blood boil.
That is all, too much is wrong to bother correcting.

 

[adroc_thurston]

Is AMD really that hard to understand?
Creating a biased argument by omission and outright misinterpretation to this degree is actually making my blood boil.
That is all, too much is wrong to bother correcting.

It's the local schizo just press the ignore button and move on.

 

[branch_suggestion]

It's the local schizo just press the ignore button and move on.

Still better than B3D I suppose.

 

[LightningDust]

9. Venice 192-core (600W) -> Vera Superchip 176-core (100W) -> Prometheus

View attachment 123608

While I am trying to create a table listing potential Vera specs, Bionics and HXL has pretty much confirmed about Venice SP7/SP8 specs and TDP. Thanks to the leaks, I have pretty good idea about Venice platform which seems confusing at first. Let's go point to point:

• First of all, there are 2 Zen6 dies: Zen6 with 12-core and 48MB L3 cache will be fabbed by N3P process, not N2 as last rumor leaked. Zen6c with 32-core and 128MB die will be fabbed by N2 process. Two Zen6 will be used for next gen client CPU; that make total 24 max core counts.
• By doubling the L3 cache, Zen6c and Zen6 should share most of the features.....except clock speed due to extra 20 cores in Zen6c. More on that later.
• SP7 platform will support 16-channel DDR5. So far there is one model leaked with 8 Zen6c die and 2 IOD. Each IOD should support 8-channel DDR thus SP7 requires 2 IODs.
• SP8 platform will support 8-channel DDR5. By cutting half of memory bandwidth, SP7 could only support up to 128 Zen6c / 96 Zen6. Yep, it is lower than Turn Dense with 12-channel memory bus.
• Here comes my understanding of TDP numbers. According to leaks, 256-core should come with 600W, each Zen6c should consume 50W and each IOD should consume 100W. That sum up total 600W.
• 96-core Zen6 with 400W: Each Zen6 should consume 40W and each IOD should consume 80W (without linking to other IOD). Total 400W.
• 128-core Zen6c with 350W: After deducting 80W IOD power, each Zen6 die should consume 67.5W which is higher than Zen6c in SP7. My thinking is AMD might try to clock Zen6c higher so that the difference between 96-core Zen6 and 128-Zen6c will be as small as possible. Thus, AMD could command higher price tag for 128-core.
• 192-core Zen6c with 600W: Bionic believe Zen6 die will be used in SP7 platform. I don't think so, there is no point putting more than 8 dies in SP7 when Zen6c is able to fit in the core counts. What we are lacking is HP Zen6c: And if we apply 67.5 with 6 dies, we get total sum of 605W. Thus, I believe AMD will use 6 Zen6c die to create high performance 192-core...

Your Vera specs massively underestimate TDP. (Also, Vera doesn't have LPDDR6, AFAIK. It has LPDDR5X and, bizarrely, DDR5, though I have no idea if the latter will be enabled in released silicon.)

 

[Tigerick]

Your Vera specs massively underestimate TDP. (Also, Vera doesn't have LPDDR6, AFAIK. It has LPDDR5X and, bizarrely, DDR5, though I have no idea if the latter will be enabled in released silicon.)

Yep, 50W is the TDP numbers given by Jensen. I suspect it means CPU cores only excluding memory controllers. I will put question marks for Vera SoC. As for memory controllers, LPDDR6 is coming real soon. Vera which is coming by end of 2026 should utilize LPDDR6, we shall see..

 

[LightningDust]

Yep, 50W is the TDP numbers given by Jensen. I suspect it means CPU cores only excluding memory controllers. I will put question marks for Vera SoC. As for memory controllers, LPDDR6 is coming real soon. Vera which is coming by end of 2026 should utilize LPDDR6, we shall see..

Believe what you wish.

 

[Cheesecake16]

Yep, 50W is the TDP numbers given by Jensen. I suspect it means CPU cores only excluding memory controllers. I will put question marks for Vera SoC. As for memory controllers, LPDDR6 is coming real soon. Vera which is coming by end of 2026 should utilize LPDDR6, we shall see..

1) I highly doubt it's 50W for just the CPU cores unless they were not very performant cores (And as we all know, Jensen would never lie... Right guys... Right?!?!)
2) Vera isn't LPDDR6, it's LPDDR5X... likely LPDDR5X-9600 on a 512b bus...

 

[Cheesecake16]

Your Vera specs massively underestimate TDP. (Also, Vera doesn't have LPDDR6, AFAIK. It has LPDDR5X and, bizarrely, DDR5, though I have no idea if the latter will be enabled in released silicon.)

I think what is going on is that Vera will support CXL on its PCIe lanes and you will be able to attach DDR5 modules to Vera via CXL.mem.
Which makes sense for Vera considering that it is just a memory expander for Rubin.