AMD's Barton Contains 512kb of L2 cache + possible MS x86-64 support **UPDATE CONFIRMED**

[grant2]

At this point in time, I don't think we need to make this jump quite yet. I just think AMD is releasing 64-bit to the consumer before its time.

Many years ago i read an article by someone who was recompiling his 16bit apps into 32bit and realizing 30% performance gains with 50% larger programs.

I don't know if the situations are analogous but i don't think many people would feel that *any*performance gain is "before its time" ...

I guess we'll see shortly if 64 bit processing really is all it's cracked up to be =)

 

[Sohcan]

<< That is what I'm saying. The proprietary processors in the low end are going to die relatively quickly; with Xeons, Itaniums, and Hammers to replace them. It is only a matter of time for the high end ones to die off as well (Bye bye multiple Sun processors, hello multiple Itanium processors). The companies IBM, HP, Sun, etc will still exist for quite some time. But they are beginning to see that pooring billions of dollars into research of these proprietary processors is not the best way to earn money (instead the service of these massive supercomputers will be the likely money maker). >>



Ah, okay, I misinterpreted your previous post....I thought you meant that large scale systems as well as the likes of IBM, Compaq, HP, etc will die out.

It is painful to say that it does appear high-end proprietary RISC is dying out....the homogenized CPU market will become quite boring from an architectural perspective.

Compaq mis-managed Alpha, and the EV7 will be the last design; they are using Itanium in the future. HP's PA-8700 is drop-in compatible with McKinley's bus architecture, and I don't think there will be any designs past Mako, after which they'll switch completely to Itanium. While it has become a strong force in the embedded market, MIPS funding has become a trickle, and SGI now primarily uses Xeons and Itaniums. I don't know how much longer IBM will maintain Power...Power4 seems to be focused at extreme high-end systems, and IBM is adopting Itanium as well.

Sun very well may be left alone in the high-end RISC market.

 

[zemus]

"block transferes one can now move twice the raw data in and out of the registers...it's probabbly about 5-15% [performance gain] depepedning on the program"
This works as long as you double the number of registers - otherwise you get a small performance decrease. More registers = more cost. At this point in time, I don't think we need to make this jump quite yet. I just think AMD is releasing 64-bit to the consumer before its time.


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Not sure where you are getting that idea from, specifically about needing more registers ( which hammer provides anyway )

Lets try again... say I wanna copy a blobk fo data somewhere, could be a string, or just some block of memory, say 4K of information. In i386, i could do this in 1000 movs in x86-64, I can do it in 500. Not exactly the most techincal way of puttin this, but heh, I am sure you understand

 

[Goi]

Does anyone know if the Barton will be compatible with current motherboards based on KT333 or the upcoming KT400 chipsets? In fact, will the Thoroughbred even be compatible? From what I've read so far the Barton is just a Thoroughbred with 512KB L2 cache rather than 256KB, since they've removed the SOI feature.

 

[MadRat]

Perhaps we are reading too much into Barton and not enough into Thoroughbred. What if Barton IS the original Thoroughbred? The long delay to release Thoroughbred would make much more sense being that the delay is AMD working on a Duron-ized version of Barton as Thoroughbred rather than a shrunken Athlon at .13 micron. The x86-64 instructions could be disabled in the Thoroughbred in order to cripple its performance.

 

[pm]

Dullard and Sohcan, this has been one of the more insightful discussions of the high-end computing industry that I have read in quite a while. I'm not going to contribute to it, but I would like to mention that I am enjoying reading it.

Patrick Mahoney
IPF Microprocessor Design Engineer
Intel Corp.