IntelUser2000
Elite Member
- Oct 14, 2003
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Intel is being really secretive now. They do mention enhancements that's beyond AES but didn't say which.
Not if we can trust that CPU-Z read-out (I'm quite sure we can trust JC. he was the first one to leak & publish nehalem numbers). Doesn't changing L2 involve a major redesign?
http://www.dvhardware.net/article34782.html
According to Wikipedia, however, Sandy Bridge is going to have 512KB L2.
Nemesis 1
Lifer
- Dec 30, 2006
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Yes I did. I may be reading to much into fact that Larrabee has to recompile X86 programs for them to operate. Since Haswell is along ways off . If most X86 programms been recompiled no need to run haswell as a Cisc backend. I see Intel going VLIW backend . As many hand helds use c/C++. If Most X86 has been already recompilled no need for decoders x86 on haswell. Intel /Apple seem to be walking hand in hand while going in differant lanes. Intels setup and snow look like made for each other . Let us also not forget about open CL. No x86 required here. If you read larrabee you will see that intel can do differant length code from long to short. How long long is I not know . But if its long enough that Cisc backend can't handle long code. So whats back there. Just cause x86 decoders are onboard doesn't mean alot when run on software layer.As intel stated the code is operating on a sowtware layer between larrabee native and frontend. Even tho sse is inplace. Your telling me That because of the past there is no future, Parrallel code is advanced enough .
Please someone pinch me . I have to be in a nightmare of misunderstandings. What is LARRABEE. Its a change to highly parrallel instructions. Why would I not believe intel would advance tech after changing X86 code threw recompile. Amd just made life easier for intel . By excepting AVX. This may move Haswell forward. I may be reading it wrong but as I understand it X86 code run a larrabbee single threaded will be faster than single threaded code on Nehalem if Os sends code to gpu. I think when you see how grand central works with Nehalem larrabee you will see more clearly. Its a hugh differance in performance up to 40%. That I have witnessed. Without using larrabee.
Why isn't Intel doing FMA until Haswell? We know they can. But they don't want those performance improvements . Either its Intel is retarded. Or Intel knows full well that FMA x86 is a bad Mix. Or many are suggesting (not here) this will give AMD back performance lead and Intel is blindly allowing to happen . Even tho they have same tech . Intel slipped back to netburst is what you would have us believe.
Ahh, Wikipedia, the most reliable source on earth.:laugh:
Anyway, does anyone realise that enthusiasts make up perhaps very little of the market, and AMD, without dramatically increasing their advertising budget and maybe creating an easy to remember slogan, will achieve very little to win sales, even if they do compete very well. Also, Bulldozer will need to improve its efficiency, HT speed and other communication speeds, power consumption, increase in core numbers, increase in cache speeds, decrease in heat output, increase in speeds per clock and hopefully be a good overclocker. Some of those things may and probably will not be achieved, but AMD would need to regain competitiveness in the CPU market at the high end by atleast excelling at something. Well, good luck AMD
Yes, Wikipedia is unrivaled, outstanding and a pretty reliable encyclopedia. Yes, they even happen to use actual sources which everyone can reliably check. In this case the article is based on some rumours from the far east -- what did you expect? Rumours are rumours. At this stage there is probably no official information about Sandy Bridge available. I'm just using those rumours to illustrate a point (i.e. westmere 256KB; sandy could be -> 512KB L2).
Yeah I trust it and JC, he was right about Nehalem all along too.
I'd think if CPU-z couldn't get the cache size right then it would either gray out the box as it does for everything else or it would display some weird result like 4KB of cache or 4GB of cache...seems unlikely it would error out and get a number that was actually ballpark close to reasonable.
So I'm really wondering just how much people-hours did Intel bother to invest into Westmere? Is it basically an optical shrink of Nehalem, sans 2 cores and associated uncore xtors to support those two cores? It's possible they just phoned this one in knowing full well AMD would have zero capability to respond for nearly a full year, at which time Intel would debut Sandy anyways.
Regarding wiki credibility...it is getting better (not worse IMO) over time but I still think this article on wiki and the mantra "trust but verify" (a famous cold-war quote by Reagan regarding nuclear disarmament treaties and the USSR) is both apropos and prudent.
What if AMD puts ZRAM in Bulldozer? ZRAM should have roughly 6x the density of traditional SRAM. AMD could use a 32MB L3 cache with a smaller footprint than the 8 MB caches they're using now. The downside is that ZRAM isn't quite as fast as SRAM.
So two questions:
Is the higher capacity of a ZRAM cache enough to offset any speed advantage of SRAM?
Will AMD finally put ZRAM technology to use?
So two questions:
Is the higher capacity of a ZRAM cache enough to offset any speed advantage of SRAM?
Will AMD finally put ZRAM technology to use?
Its called a friggen Bulldozer of course it has a chance
Seriously though AMD will compete maybe not at the high price point but they usually have the cheaper and faster mid range chips.
Seriously though AMD will compete maybe not at the high price point but they usually have the cheaper and faster mid range chips.
Nemesis 1
Lifer
- Dec 30, 2006
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Hows that. Intel has C2D as low end mid range now. When Sandy arrivies Inyels lowend and mid will be Westmere type CPUs.
XS has a thread going on AVX with 2 fanbois battling it out. The one guy hasn't been right about anything in at least 3 years . The other doesn't No what info to post to debunk the other.
Point is Intel AVX and AMD AVX tho compatiable. Do nor share SAME Capabilities Intel can do SSE2 with a Prefix of vex for recompile and app. speedup . Intel Left NO space for AMD to do this . As AMD had Announced SSE5 . So Intel left ZERO room for AMD . Now AMD have to talk this out as Intel IP is new. Than it gets more interseting.
AMDs lawsuite Against Intel . Intels new lawsuite against AMD . AMD thinking they can just copy intels IP AVX isn't correct. Its intels If you read intels paper on it . Prefix of sse2 with Vex is intel EXCLUSIVE . AMD /Intel have to have agreement. I don't see Intel giving AMD this IP as a license. Why should they? I want to see both companies go seperate routes. I was going to post over at XS to end arguement . But I don't like either fanboy. Not that theres alot of people Ilike on line. 2 I do like Are idontcare/ duvie. Now these 2 guys are way differant . But both have fine qualities. Duvie doesn't post enough.
XS has a thread going on AVX with 2 fanbois battling it out. The one guy hasn't been right about anything in at least 3 years . The other doesn't No what info to post to debunk the other.
Point is Intel AVX and AMD AVX tho compatiable. Do nor share SAME Capabilities Intel can do SSE2 with a Prefix of vex for recompile and app. speedup . Intel Left NO space for AMD to do this . As AMD had Announced SSE5 . So Intel left ZERO room for AMD . Now AMD have to talk this out as Intel IP is new. Than it gets more interseting.
AMDs lawsuite Against Intel . Intels new lawsuite against AMD . AMD thinking they can just copy intels IP AVX isn't correct. Its intels If you read intels paper on it . Prefix of sse2 with Vex is intel EXCLUSIVE . AMD /Intel have to have agreement. I don't see Intel giving AMD this IP as a license. Why should they? I want to see both companies go seperate routes. I was going to post over at XS to end arguement . But I don't like either fanboy. Not that theres alot of people Ilike on line. 2 I do like Are idontcare/ duvie. Now these 2 guys are way differant . But both have fine qualities. Duvie doesn't post enough.
Shintai (at XS) is trying to become the biggest moron on the Internet, and you're not doing yourself a favor for believing him. It's pretty clear what AMD has stated regarding AVX. They will support it FULLY and in addition they are adding some of the former and now defunct SSE5 (including FMA4) as a superset of AVX calling it XOP now instead. They did the same thing with SSE(x) adding SSE4a as a superset of (up to) SSE3. I doubt AMD will get much software support for XOP though, but any code that is compiled for Sandy Bridge+AVX will run on Bulldozer period.
In addition AMD has indicated that they will add Intel's version of FMA later once the spec becomes finalised, but it seems unlikely it will arrive with the first version of Bulldozer. BTW this could be the main reason why Bulldozer has gotten so delayed. AMD needed time to implement AVX which would not be a trivial thing on a design already well under way.
Nemesis 1
Lifer
- Dec 30, 2006
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I don't believe Shiintel . I said he doesn't know how to debunk what informal said. I already posted the paper here and bolded the exclusive part. So I won't bother reposting.
I said AMD will support AVX compatabilities. That not the same as capabilities. Yntil someone can dedunk what stated in Intels papers about prefix of sse2 with vec . Is an Intel exclusive.
What does it all mean?
It means intel can speed up SSE instructions by as much as 2x. AMD can only do SSE the same as always . Which in this case means Intel will be able to do SSE instructions 2x as fast as AMDs AVX. Now were FMA plays into this I not sure. Amd has to prove they can make FMA work on X86 first. I am sure it will work somewhat but Sun had all sorts of problems still not fixed.
AMD wants to win a "core race"? 16 cores on the Bulldozer? What are people going to do with all those cores? I'm being serious.
IntelUser2000
Elite Member
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Now I think about it, I think lowering the L1 cache latency from 4 to 3 cycles will have bigger impact than doubling L2 cache while maintaining the same 11 cycle latency. They must have sacrificed something when they went to static circuitry in Nehalem, and I speculate the increased L1 cache latency is one of them. The rumors of Westmere do mention "Cache enhancements", so while the capacity haven't increased, latency might have.
I still expect ~7% increase that Penryn brought over Merom with Westmere in comparion with Nehalem.
Presumably the same thing they'd do with it if it was a single-core 30GHz chip...run some computationally intentsive application that needs the speed of the day and thusly is compiled by the producer to best extract the performance available at that time.
What application is that? I don't know, super pi maybe? :laugh:
IntelUser2000
Elite Member
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16 cores in server is not a problem because they can take advantage of it better than we do. By the time 16 cores are in servers average core count for the high end desktop system is still going to be 6. We aren't even going to see 8 until few years after that.
But with 30GHz CPU at least everything will be faster, unlike multi-core. Too bad that's not reality or else neither AMD or Intel would have went multi core.
But with 30GHz CPU at least everything will be faster, unlike multi-core. Too bad that's not reality or else neither AMD or Intel would have went multi core.
Nemesis 1
Lifer
- Dec 30, 2006
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idontcare In older papers intel stated that Nehalem was designed from the ground up for 32nm prosess. Were as c2d was designed for 65nm. 45nm was intels effort at getting 1 more gen out of old tech Than on top of that,they addedhighK/Metal gates great effort. . They did well. So I am saying 10-20% gains. clock for clock. on overclocking . If intel brings out anything other than 3.0ghz and below I would be shocked. Basicly the 2 core 32nm. is going to give the old intel 4 cores fits. Amd hasn't anything to match. Fact is AMD coming out with 2 core PHII is a hugh mistake, Unless amd is going to put them in crackerjack boxes as prizes.
IntelUser2000
Elite Member
- Oct 14, 2003
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Nemesis 1, english isn't your strength I take. "10-20% gains per clock on overclocking" doesn't make sense.
What part of full AVX support don't you understand? Most SSE instructions were simply ported over to AVX and some new ones were added. AMD needs to support all of that if they can claim compatibility.
Yeah I'd agree with that decision. Looking at how much Phenom really needed 45nm to enable the sram density necessary to hit the 2MB cache/core needed for their chips combined with hitting 3GHz clockspeeds I would not have wanted to see BD cut-down and shoehorned into the kind of diesize footprint and xtor budget that 45nm would have required for a cost-viable chip.
65nm was just not enough to enable Phenom architecture to go where it needed. 45nm no doubt would have put BD in the same situation.
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