AMD Torrenza

[fzkl]

Anyone has any information on how the co processor sitting on the hypertransport bus is going to access memory?

Are the proc and the co-proc gonna share common memory in which case i suppose memory transactions happen from co-proc to proc to memory controller to memory module?

Or would it be necessary for the co-proc to have its own mem controller to access its own memory?

 

[Lord Evermore]

It could probably be done either way, depending on how dependent a co-processor is on fast memory access, with no latencies due to the controller having to handle main memory access, or expense. If a co-processor gets a memory controller designed into it, there'd be no reason it couldn't access the memory slots connected to that socket. For a cheaper system, let it access the memory via the CPU. This could be a way for manufacturers to segment the market, selling co-processors with the memory controller disabled/broken for a little less money.

With a proper system, the co-processor and CPU would communicate directly over HyperTransport, so the performance difference would probably be minimal, unless the CPU and main memory controller were already being heavily accessed, so that the co-processor would be fighting for time with the memory.