FD-SOI can be cheaper than bulk.
The Substrate cost (wafer) is higher than a bulk-Si but Litho and FEOL process steps are less making the FD-SOI cheaper overall.
Keyphrase in the first sentence is "can be".
Yes it can be cheaper if the engineers developing the bulk-Si process do silly things to make the bulk process much more expensive (no limit there) or if the engineers developing the FD-SOI process hit upon a stroke of genius and make their process cleverly lower in cost over that of the process developed by the competition.
This does happen by the way, there is fierce patent competition to develop integration of electrical components with the fewest mask-adders possible...developing a
mimcap which is 1-mask adder versus say a mimcap that is 2-mask adder for example.
So the lead in process simplicity that the FD-SOI team has can easily be blown in terms of overall cost/wafer if the production fab itself is running at slightly slower cycle-time or has intrinsically slightly higher defect density (D0).
In the end, because of all the contributing factors that go into cost/wafer, we never have real-world examples of apples-to-apples comparisons except when a fab like IBM's fishkill runs both flavors of a
node at the same time.
ARM Announces 45nm SOI Test Chip Results That Demonstrate Potential 40 Percent Power Savings Over Bulk Process
The silicon results show that 45nm high-performance SOI technology can provide up to 40 percent power savings and a 7 percent circuit area reduction compared to bulk CMOS low-power technology, operating at the same speed. This same implementation also demonstrated 20 percent higher operating frequency capability over bulk while saving 30 percent in total power in specific test applications.
The problem is that what we do have evidence of in the real-world is that (1) TSMC is the only foundry to have made money in the entire history foundry business and they have determined that SOI is not viable for their business model, and (2) the other major user of SOI was AMD and they too failed to financially capture success with their reliance on SOI whereas Intel's reliance on Bulk-Si certaintly did not lead to its financial undoing.
So this seems to be a case of theory versus practice. In theory there is no difference between theory and practice, but in practice there is.
It seams to me that the difference is only in the wafer. AMD can purchase ready FD-SOI wafers.
Can AMD or any other use the same 28nm process at GloFo but use FD-SOI wafers ???
Im asking because the transistors will be created over the FD-SOI Thin undoped body.
Yes, but...the but part comes in in that the layout of any given IC is going to be specifically optimized for the nuances and tradeoffs that come with the overall chip properties, both electrical and thermal.
So while AMD surely could in theory reuse the same maskset with an FDSOI wafer substrate as they would for a bulk-Si substrate, they would be fools to do so and not take advantage of any layout optimizations that ought to be done in porting one design for the other.
After all, the parametrics would change, electrostatics and all that, upon substitution of the FDSOI wafer for the bulk-Si wafer (if the parametrics did not change then why use the more expensive FDSOI wafer?). As soon as those parametrics change then so to do all the integrated circuit function, timings and so on.
You risk taking a design that yields at say 4GHz on bulk-Si and ending up with a design that has to be clocked at a lowly 1GHz on FDSOI for instance, but if you redo the maskset and layout work (a year minimum lead-time once you factor in validation) then you might get back to a 4GHz product but with lower power-consumption as the benefit.
Basically what this boils down to is that in practice, if you are going to use FDSOI at 14nm then you need to have already decided that today and be in the process of designing your chips with that expectation in mind.