Originally posted by: myocardia
From your experience, what are the possible performance gains from one stepping/revision, to another? You'd know alot more about that than we would, since you've "played around" with steppings that never saw the light of day, unlike us. From what I read, they usually seem to be almost nonexistant, at least on a clock-for-clock basis. Overclocking is obviously an entirely different matter.
I'm not the best person to try and explain this, but let me hack away at it.
Progressive steppings are designed to fix things that were broken or undesirable on prior steppings. Typically the performance improvement to be gained from stepping is more about eliminating or mitigating something that was imparting performance degradation in an earlier stepping.
When significant things are broken, i.e. substantial performance degradation, then that stepping won't be considered retail worthy. It will be respun and a new stepping released. If the broken stuff is insignificant (performance wise) then patch around the problem with microcode (some performance penalty) and ship the chips while prep'ing a new stepping.
So yes, in the retail space the performance impact of successive steppings is generally zero or near zero as typically the initial stepping released to retail doesn't contain anything seriously broken and waiting to be fixed in a subsequent stepping. (AMD's TLB bug is an exception to this)
Where things get choppy is when you get folks making performance analyses from steppings that the manufacturer considers to have substantial flaws to the extent that the stepping is not going to ship for revenue.
Sometimes these steppings can simply be speedpath limited (thus no clockspeed worthy SKU's to sell) so the IPC is there but the raw-GHz is lacking. Such steppings provide an OK window into future performance when scaled properly.
But more often (in my narrow experience with 486 cpus (yeah, that long ago) and more recently SUN microprocessors) these pre-release steppings will contain a number of functional block issues as well as cache issues that really rely on fuses getting blown and the chip's functionality really relying on a faulty stepping being fixed up enough to boot and test out the rest of the system's functionality.
We don't know where the early Deneb chips fall in these extremes. This is what people refer to when they speak to the
health of the silicon. But in this case we have pre-release steppings giving 8% IPC improvements where AMD spokespeople are saying the retail stepping will deliver 15-20%. So I am inclined to believe the spokespeople until data (i.e. tests on a retail stepping) prove the them wrong.
Yes its AMD, yes they have credibility issues from Phenom, but these are not the same people involved with the Phenom marketing hype.
Originally posted by: Martimus
I really have no experience with revisions of silicon. I mostly worked in Power Supply circuitry and Three-Phase Electric Motors when I worked in design. I could liken it to design iterations that fixed problems and improved performance on those.
The process is identical. Iterative. At TI we called them learning cycles. No doubt every company has their own vernacular for its description. But the thinking behind it is the same everywhere in every industry. We are all human after all. Mostly.
But as you know, not all improvements are the kind the customer thinks you are busy working on. Reliability for instance. We all assume Intel and AMD are just taking care of reliability in the background, we buy chips based on IPC x GHz and not on reliability.
So a stepping that takes care of a reliability issue would appear to us as a yawner because the "performance" impact is negligible. But a stepping that fixes a cache bug (a TLB one for instance
) could actually result in a sizable performance impact of the kind that would get our attention.
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