AMD Ryzen (Summit Ridge) Benchmarks Thread (use new thread)

[sirmo]

It is pretty hard for someone to pull a fake result out of their arse, when there is valid information included that hasn't been previously leaked.

like?

 

[blublub]

So I guess the process is:
1. Acquire AMD ES CPU
2. Short AMD
3. Cripple L3 Cache, lock at base clock
4. Post terrible benchmark
5. Profit

LoL - yeah it's a possibility. But if I am not mistaken now AMD show to have a CPU with more cores than Intel - even if it is barely running - so I doubt shares are going south, either nothing happens or it is a trigger to go past 8$(but I doubt the latter)

 

[IEC]

64 cores... o.o

 

[The Stilt]

like?

Like the ES SKU and the codename for the 2P CRB.
The person who posted that score definitely has the system available. Only the used configuration for the system remains questionable.

 

[superstition]

Memory speed seems to check out.

http://www.corsair.com/en-us/blog/2014/september/ddr3_vs_ddr4_synthetic

 

[Tuna-Fish]

Hard to believe that L3 would account for > 43% difference to Haswell thou

If the L3 cache is really disabled, I find this difference completely believable. With no L3, the chip would have only 512kB of effective data cache. There are several subtests which would not fit in this, but would fit in a few-MB cache. The performance difference in these subtests should not be ~50%, it should be something like 400%.

Of course, the lack of L3 might just be GB reporting error.

 

[The Stilt]

If the L3 cache is really disabled, I find this difference completely believable. With no L3, the chip would have only 512kB of effective data cache. There are several subtests which would not fit in this, but would fit in a few-MB cache. The performance difference in these subtests should not be ~50%, it should be something like 400%.

Of course, the lack of L3 might just be GB reporting error.

Zen should be able to work without the L3 without having a huge performance penalty. After all the standard L3 configurations are 8MB, 4MB or 0MB per CCX.

 

[inf64]

It is obvious the scores are way too low hence it makes no sense to try and draw any conclusions on Zen based on them.

 

[Arachnotronic]

It is obvious the scores are way too low hence it makes no sense to try and draw any conclusions on Zen based on them.

Multithreaded score looks too low, but single core score looks reasonable.

 

[inf64]

Multithreaded score looks too low, but single core score looks reasonable.

ST looks OK if you assume Turbo was off and the cores ran at fixed base clock.

 

[Arachnotronic]

ST looks OK if you assume Turbo was off and the cores ran at fixed base clock.

yeah, I'm assuming that ST score is turbo off, running at 1.44GHz.

 

[raghu78]

With AMD its best to not assume anything and just wait for product launch and reviews at launch. AMD has disappointed too many times in the past to take marketing & PR talk seriously.

 

[jpiniero]

It really ought to be at least 30% faster in ST and 3X in MT, even without the turbo. I suspect it's running in quad channel mode, and that and the GMI is screwy/not done yet.

Celeron 1007U (Ivy Bridge, 1.5 Ghz) gets ~1500 on the ST score. Celeron 877 (Sandy Bridge, 1.4 Ghz) gets ~1350.

 

[Abwx]

Well ST score if it was achieved at 1.4Ghz is OK I suppose (~16% behind Broadwell EP per clock). MT score is just awful for some reason.

MT score scale about 38x in LZMA but the RAM bandwith, wich is very low, is accounted in the total scaling, and because the MT RAM bandwith is lower than the ST RAM bandwith this make a scaling lower than 1 that is added to the total, same thing for all tests that rely on bandwith and wich wont scale accordingly in MT.

Edit : This is assuming that the thing is legit as there s some weirdos ST numbers comparatively to PD or Steamroller.

 

[StinkyPinky]

So basically the IPC will be lower so in the hope of making up for it, they will tack on more cores which will ramp up the TDP? That sounds somewhat familiar.

 

[itsmydamnation]

you dont know what clock it is running at 1.44 is just the

So basically the IPC will be lower so in the hope of making up for it, they will tack on more cores which will ramp up the TDP? That sounds somewhat familiar.

NO............

 

[Abwx]

So basically the IPC will be lower so in the hope of making up for it, they will tack on more cores which will ramp up the TDP? That sounds somewhat familiar.

What sound familiar is the negative content of your post...

Now if i was to use Kabini as comparison and Cinebench 11.5 as metric this would point to a score of 2 at 4GHz, for instance Kabylake score about 1.92 at this frequency, so there s a lot of things in those numbers, depending of the comparison..

Other than this the fact that MT bandwith is lower than ST bandwith is an indication that the RAM frequency was drastically reduced for the MT test, that s correlated by other submissions, here the MT bandwith is half the one of an FX6300, ST bandwith is roughly 30% lower, not sure that these figures are adeqate for a 32C CPU that is supposed to use DDR4...

 

[superstition]

Other than this the fact that MT bandwith is lower than ST bandwith is an indication that the RAM frequency was drastically reduced for the MT test

Interesting. My first thought was that RAM gimping would be the easiest way to post low results (a tried a true tactic when we look at OEMs and APUs). But I looked at that Corsair article and it seemed like the numbers were reasonable.

 

[Dresdenboy]

AMD has several patents mentioning directory based cache coherency, which uses the L3. If it were disabled, that method might fall flat on its face by doing a lot of asking around for any memory request not hitting L2 or using shared cache lines. With distributed memory controllers, this might even happen a lot on a single processor through the GMI links.

A CCX's chance to hit local memory would be 1/16.

 

[Sweepr]

http://www.pcper.com/news/Processors/Leaked-Geekbench-Results-AMD-Zen-Performance-Extrapolated

 

[Nothingness]

Scaling down score puts higher clocked systems at a disadvantage due to memory. So this might be even worse for Zen than what is shown here. I hope final results will be better.

 

[The Stilt]

I'm pretty sure the results are lower than they will normally be. Either due a non-standard configuration (debug mode or lower than default clocks) or due a issue with the software stack. I'm expecting the average IPC to match Sandy / Ivy Bridge, so if the performance would this bad it would definitely be a surprise even to myself. At this point AMD should be bringing up the software stack (AGESA, microcode, co-processor firmwares), so they might want to log the CPU behavior pretty intensively. Some of the debug methods (e.g. full monitoring though eng. sandbox) can cause up to 20% performance hit. However I wouldn't expect AMD themselves to make this kind of mistake and publish a Geekbench result, which makes me believe that the leak came from a partner (i.e PRC most likely). And partners of course don't do the kind of debug I mentioned.

 

[Abwx]

http://www.pcper.com/news/Processors/Leaked-Geekbench-Results-AMD-Zen-Performance-Extrapolated

I guess that PCPER inability to look further did gave you great hopes, indeed here to comfort your expectations, that is, this alleged Zen core has about the same IPC as Kabini in many of thoses ST tests, one has to wonder why AMD did bother to design such a big core just to equate what they already have at hand since years..


http://browser.primatelabs.com/v4/cpu/225444

http://browser.primatelabs.com/v4/cpu/105227

Edit : Rather than concluding like the pseudo journalist at PCPer that Zen has 70% of IB IPC one who has a few clues, and given Kabini s numbers, would conclude that the chip is eventually running at 1GHz...

However I wouldn't expect AMD themselves to make this kind of mistake and publish a Geekbench result, which makes me believe that the leak came from a partner (i.e PRC most likely). And partners of course don't do the kind of debug I mentioned.

In principle due to NDAs no partner has the right to to such a test publicly, and moreover, without even retrieving it after a short time, wich point eventualy to some willfull action, and certainly not to prop up AMD.

 

[TheELF]

I guess that PCPER inability to look further did gave you great hopes, indeed here to comfort your expectations, that is, this alleged Zen core has about the same IPC as Kabini in many of thoses ST tests, one has to wonder why AMD did bother to design such a big core just to equate what they already have at hand since years..

Who told you that it's "such a big" core?
AMD said 40% higher then EX core,but zen cores have SMT (NOT hyperthreading) so they could end up with one SMT core being 140% EX divided by 2 = one ZEN (smt) core = 70% of one EX core.

AMD made a server CPU,low power/high performance (within that power envelope) that can be scaled down to work as the next console CPU/APU,none of which points to a "such a big" core everything points to a small core,but time will tell we need real benchmarks and not everydudes napkin calculations on how it might be.

 

[Abwx]

Who told you that it's "such a big" core?.

The diagrams published by AMD say so, it has been discussed ad nauseam , basically a Zen core is twice an EXV core and has the full FPU of a module.

AMD said 40% higher then EX core,but zen cores have SMT (NOT hyperthreading) so they could end up with one SMT core being 140% EX divided by 2 = one ZEN (smt) core = 70% of one EX core..

And AMD also said at Hot chips that those 40% are without SMT, so either you make some howework or else you are just making the thread being redundant with the same useless questions that have been answered long before..

but time will tell we need real benchmarks and not everydudes napkin calculations on how it might be.

The only real bench, and with a fully functional chip, was the blender rendering made by AMD, but seems that the result they displayed didnt please everybody by here..