AMD Ryzen (Summit Ridge) Benchmarks Thread (use new thread)

[Sweepr]

Zen Lead Architect Michael Clark's Hot Chips "official" presentation

https://www.youtube.com/watch?v=Ln9WKPEHm4w#t=01h01m45s

 

[krumme]

Starts 1:02. All known stuff ofcource as its august material. Some interesting questions a 1:33 forward.
New horizon is more interesting. For basic arch info go read AT piece of it imo.

 

[Doom2pro]

So it was fake all along... Go figure. Well maybe next time a "leak" pops up they will have to provide more details to get taken seriously. I find it odd how certain Intel favoring people are holding on to this fake leak with such hope that it may still be actually real... Don't they want competition and lower prices? Sigh whatever.

 

[PhonakV30]

Can you tell me how did you find out? i have problem with browsing Youtube.

 

[krumme]

Sweepr
New Horizon presentation is here
https://m.youtube.com/watch?v=4DEfj2MRLtA
Better put that top and embedded in op

Info starts 0:27

 

[blublub]

Zen Lead Architect Michael Clark's Hot Chips "official" presentation

https://www.youtube.com/watch?v=Ln9WKPEHm4w#t=01h01m45s

Funny thing is that most sites/articles list Jim Keller as lead architect although he wasn't - though I don't know what JK's position in regard to ZEN was and if JK ever was a solely lead architect, he just seems to come, work a bit an then leave..

 

[rvborgh]

Hi DresdenBoy... for what its worth, i did some runs out to 48 cores for you for Blender, CB R15, and CB 11.5... on my K10 based quad Opteron, as well as some runs on my 4770, and 5930K... perhaps some high core count Xeon folks could do some runs to develop some sort of relationship between things. i didn't do single cores as it would have taken forever. 4 core runs were bad enough lol. hopefully info like this can be used to estimate Zen performance from the Blender run.

Blender with Ryzen file

04 threads at 3.0 Ghz 150 samples: 3:24:77 seconds
08 threads at 3.0 Ghz 150 samples: 1:42:87 seconds
12 threads at 3.0 Ghz 150 samples: 1:09.25 seconds
16 threads at 3.0 Ghz 150 samples: 54.11 seconds
20 threads at 3.0 Ghz 150 samples: 42.18 seconds
24 threads at 3.0 Ghz 150 samples: 35.67 seconds
28 threads at 3.0 Ghz 150 samples: 30.83 seconds
32 threads at 3.0 Ghz 150 samples: 27.06 seconds
36 threads at 3.0 Ghz 150 samples: 24.34 seconds
40 threads at 3.0 Ghz 150 samples: 22.08 seconds
44 threads at 3.0 Ghz 150 samples: 20.36 seconds
48 threads at 3.0 Ghz 150 samples: 18.80 seconds

additional:
16 threads at 3.4 Ghz: 46.99 seconds

CB R15

04 threads at 3.0 Ghz: 298cb
08 threads at 3.0 Ghz: 584cb
12 threads at 3.0 Ghz: 860cb
16 threads at 3.0 Ghz: 1132cb
20 threads at 3.0 Ghz: 1396cb
24 threads at 3.0 Ghz: 1652cb
28 threads at 3.0 Ghz: 1893cb
32 threads at 3.0 Ghz: 2149cb
36 threads at 3.0 Ghz: 2376cb
40 threads at 3.0 Ghz: 2607cb
44 threads at 3.0 Ghz: 2831cb
48 threads at 3.0 Ghz: 3074cb

additional:
04 threads at 3.6 Ghz: 330cb
24 threads at 2.5 Ghz: 1440cb

i7-4770 (non K) at stock (4C/8T): 748cb
i7-5930k at stock (6C/12T): 1070cb

4 threads at 3.6 Ghz: 330cb

CB 11.5

04 threads at 3.0 Ghz: 3.51
08 threads at 3.0 Ghz: 6.90
12 threads at 3.0 Ghz: 10.28
16 threads at 3.0 Ghz: 13.59
20 threads at 3.0 Ghz: 16.75
24 threads at 3.0 Ghz: 19.92
28 threads at 3.0 Ghz: 22.95
32 threads at 3.0 Ghz: 25.83
36 threads at 3.0 Ghz: 28.91
40 threads at 3.0 Ghz: 31.65
44 threads at 3.0 Ghz: 34.66
48 threads at 3.0 Ghz: 37.02

additional:
4 threads at 3.6 Ghz: 4.01
8 threads at 3.3 Ghz: 7.49 (simulated Phenom X8)
16 threads at 3.6 Ghz: 16.0
48 threads at 3.1 Ghz: 38.26
48 threads at 3.2 Ghz: 39.04

i7-5930k at stock (6C/12T): 11.69

Is there some correlation between CB15 and Blender scores? This would put at least some credibility behind this score. Otherwise we might discuss until retail availability.

 

[krumme]

We have to remember they say a quarter of the performance uplift in zen is due to the prediction...

 

[krumme]

Funny thing is that most sites/articles list Jim Keller as lead architect although he wasn't - though I don't know what JK's position in regard to ZEN was and if JK ever was a solely lead architect, he just seems to come, work a bit an then leave..

Jim Keller was the head of the cpu group. So the boss for Clark i asume

"Jim's official title is Corporate Vice President and Chief Architect for CPU Cores, and he will report directly to Mark Papermaster. "

 

[prtskg]

http://www.overclock.net/t/1617227/...eview-on-12-13-at-3-pm-cst/1590#post_25723234
Motherboard pics by cortexa99

 

[sirmo]

We have to remember they say a quarter of the performance uplift in zen is due to the prediction...

An improved branch predictor is certainly a good way to improve performance. As it boosts performance while also saving power. It also reduces the penalty of having a deeper pipeline which is essential in reaching high clocks.

 

[Doom2pro]

GA-AX370? Sounds like my next motherboard

 

[krumme]

Jim Keller was the head of the cpu group. So the boss for Clark i asume

"Jim's official title is Corporate Vice President and Chief Architect for CPU Cores, and he will report directly to Mark Papermaster. "

Guys like Clark have so much experience they dont need a manager so to speak. He doesnt strike me as a manager type but the guy who knows his technical stuff to the smallest details. His experience and knowledge of other key persons in Amd must be huge.
Actually i think Suzanne Plummer was formally used as a director of the design so she was Clark boss. And her boss was then Keller whos bos was Papermaster whos boss was Lisa Su. Lol. So actually a long string of technical competent people.
But the beef is at clark-keller.

I think Keller was given that position not because he wanted to manage but to get what he meant was right without all kinds of managerial nonsense preventing him from getting it. Be it decicions, tech or people. To keep focus on the purpose (cpu design) and not all other crap that floats in big organizations.

 

[Doom2pro]

Guys like Clark have so much experience they dont need a manager so to speak. He doesnt strike me as a manager type but the guy who knows his technical stuff to the smallest details. His experience and knowledge of other key persons in Amd must be huge.
Actually i think Suzanne Plummer was formally used as a director of the design so she was Clark boss. And her boss was then Keller whos bos was Papermaster whos boss was Lisa Su. Lol. So actually a long string of technical competent people.
But the beef is at clark-keller.

I think Keller was given that position not because he wanted to manage but to get what he meant was right without all kinds of mangerial nonsense preventing him from getting it. Be it decicions tech or people. To keep focus on the purpose and not all other crap that floats in big org.

I'd rather it be Keller in that big brother position than some overpaid redacted who doesn't know what he's doing trying to influence every step of the design to try and stay relevant.




No profanity in tech.


esquared
Anandtech Forum Director

 

[gammaray]

do we know what the AM4 chipset/socket will include?

 

[sirmo]

Guys like Clark have so much experience they dont need a manager so to speak. He doesnt strike me as a manager type but the guy who knows his technical stuff to the smallest details. His experience and knowledge of other key persons in Amd must be huge.
Actually i think Suzanne Plummer was formally used as a director of the design so she was Clark boss. And her boss was then Keller whos bos was Papermaster whos boss was Lisa Su. Lol. So actually a long string of technical competent people.
But the beef is at clark-keller.

I think Keller was given that position not because he wanted to manage but to get what he meant was right without all kinds of managerial nonsense preventing him from getting it. Be it decicions, tech or people. To keep focus on the purpose (cpu design) and not all other crap that floats in big organizations.

What I got from that panel while back with Keller and Papermaster was that his main task was putting the teams together and implementing a new design methodology. Clark sort of touches on it with tools, and having power analysis being part of the early design stages. Not surprising considering Keller's prior employment with Apple.

Software development has gone through sort of a revolution in the last decade or so with CI CD. Continuous Integration and Continuous Deployment. Which means every revision of a codebase is automatically built, deployed and tested automatically in a matter of minutes (continuous build and test), so that the developers have constant view of the end result. Which allows for quick iterations on the design. Similarly having the constant automated validations with tools when you work on the CPU design from early on can influence the right decisions. It also give you a freedom to try things you otherwise wouldn't have time to test. Clark specifically touches on this when it comes to power, and how comparatively speaking with Bulldozer they were blind to that aspect of the design, early on.

We don't even have to look at Zen to see this in action. Just look at Carrizo and in my opinion very underrated results AMD was able to achieve there with the Dozer arch.

 

[Nothingness]

Are you sure its not just because its truly decoupled? And i mean -truly- decoupled?

Edit. Btw not sure your predictor have been trained for longer than mine. At least i hope for your case its not so but hey perhaps its just difficult to assess the quality of the predictor on a 4 stage inorder non superscalar core.

Well it depends on whether you've been working in various chip design teams for the last 20 years

 

[krumme]

Well it depends on whether you've been working in various chip design teams for the last 20 years

If you have to ask for that to know the answer you need a reboot and change the predictor. Thats for sure. Take care the next 20 years is not 20 times 1 year then

 

[krumme]

I'd rather it be Keller in that big brother position than some overpaid a$shat who doesn't know what he's doing trying to influence every step of the design to try and stay relevant.

Look at Dirk Meyers. Its not that simple. Imo hi was promoted to a position where he didnt have the business heft and at the same time he probably lost the technical touch.
Keller obviously proved at Apple he got the touch. And developed it. We will soon see.

 

[PhonakV30]

Ok finally Source of Chinese forum for that Fake Bench.

http://tieba.baidu.com/p/4905933330ctu

Title is

|推测| 对于刚刚那个“zen曝光”贴，没必要唱衰

Translate : | Speculation | just for that "zen exposure" paste, no need to bad-mouthing

another said ( this Link )

That moderator said: that op did some trick to the image. Second, the two score should be no way coming from 1 CPU. Last reason is that, moderator know someone working at ASUS. And he said ASUS have not started to produce the motherboard for Zen yet and ASUS dont know much about Zen model .So there is no way that guy get it b4 the board maker .

EDIT: I am just translating what they said.

 

[jhu]

Here's my Ryzen.blend results:

Xeon E5 2670 x2 (3.0 GHz turbo)
FreeBSD 11.0
Blender 2.76, 150 samples (total samples = 800*800*150)

1 core:   7 minutes 42.86 seconds     69135 samples/s/core/GHz
2 cores: 3 minutes 52.16 seconds      68918 samples/s/core/GHz
4 cores: 1 minute 57.42 seconds       68131 samples/s/core/GHz
8 cores: 59.99 seconds                66678 samples/s/core/GHz
16 cores: 31.40 seconds               63694 samples/s/core/GHz

1 core, 2 threads: 6 minutes 14.92 seconds   85352 samples/s/core/GHz
16 core, 32 threads: 26.31 seconds           76017 samples/s/core/GHz

04 threads at 3.0 Ghz 150 samples: 3:24:77 seconds - 39068 samples/s/core/GHz
08 threads at 3.0 Ghz 150 samples: 1:42:87 seconds - 38884 samples/s/core/GHz
12 threads at 3.0 Ghz 150 samples: 1:09.25 seconds - 38507 samples/s/core/GHz
24 threads at 3.0 Ghz 150 samples:   35.67 seconds - 37380 samples/s/core/GHz
48 threads at 3.0 Ghz 150 samples:   18.80 seconds - 35461 samples/s/core/GHz

I took the liberty of adding samples/s since that makes quantification easier. Looks like our systems have about 10% decrease in IPC from low cores to max cores.

 

[krumme]

What I got from that panel while back with Keller and Papermaster was that his main task was putting the teams together and implementing a new design methodology. Klark sort of touches on it with tools, and having power analysis being part of the early design stages. Not surprising considering Keller's prior employment with Apple.

Software development has gone through sort of a revolution in the last decade or so with CI CD. Continuous Integration and Continuous Deployment. Which means every revision of a codebase is automatically built, deployed and tested automatically in a matter of minutes (continuous build and test), so that the developers have constant view of the end result. Which allows for quick iterations on the design. Similarly having the constant automated validations with tools when you work on the CPU design from early on can influence the right decisions. It also give you a freedom to try things you otherwise wouldn't have time to test. Clark specifically touches on this when it comes to power, and how comparatively speaking with Bulldozer they were blind to that aspect of the design, early on.

We don't even have to look at Zen to see this in action. Just look at Carrizo and in my opinion very underrated results AMD was able to achieve there with the Dozer arch.

I also view it as there is wide range of tools as eg CI CD making it easier to run a big company. The portfolio of tools have expanded for years. Take a simple tools as email as an example. It wasnt widespread just 25 years ago.
It also demands specialist to implement those tools. So in many ways it gives the huge coorp better compettiveness vs prior decades. We will see more monopolization for that reason so its nice to see that it sometimes is possible for nr 2 to strike back.

 

[bjt2]

Zen Lead Architect Michael Clark's Hot Chips "official" presentation

https://www.youtube.com/watch?v=Ln9WKPEHm4w#t=01h01m45s

Awesome... Also the q&a session!

If i understood well, int and fp retire are separate and zen can retire 8+8uop/cycle.
other things: the microcode rom is between uop queue and dispatch and in the q&a the guy confirms my suspects: the decoder give only the pointer to the entry point in the ucode rom and in the uop cache it's stored only the pointer and not all the uops, that are expanded ont the fly when needed. less space. Then the label "4 instr/cycle" on the decoder makes more sense: can the decoders also decode 4 microcoded uops/cycle? It has only to give the starting pointer!

 

[DrMrLordX]

Isn't that about exactly what everyone's been saying for years now? Including AMD?

No.

Looks like it was a fake:

Thanks for due diligence to you and behrouz. That isn't the first fake leak, and it probably won't be the last . . .

If you click on a username, in the popup, you have access to ignore functionality.

Might be worth doing if you think someone is being blatantly biased and you want to filter out their posts.

Unfortunately, that is a problem when the person to be ignored happens to be the OP and an active participant in a "main benchmark thread".

 

[sirmo]

Zen Lead Architect Michael Clark's Hot Chips "official" presentation

https://www.youtube.com/watch?v=Ln9WKPEHm4w#t=01h01m45s

Man that Intel guy at the end, didn't even say thank you. Kind of rude if you ask me.