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AMD Publishes Zen 2 Compiler Patch "znver2" Exposing Some New Instructions


Senior member
Feb 4, 2013

With GCC 9 feature development ending in November, AMD today sent out their first patch enabling Zen 2 support in the GNU Compiler Collection via the new "znver2" target.

This is the basic patch introducing the next-generation AMD Zen CPU to the GCC compiler collection. At this stage it's just the basic implementation and carries over the same cost tables and scheduler data from Znver1. So it doesn't reveal any major breakthrough changes, but in digging through the code, it does confirm some new CPU instructions that will be supported by these next-gen Zen CPUs... On top of the Znver1 instructions, Zen 2 is adding:

- Cache Line Write Back (CLWB)

- Read Processor ID (RDPID)

- Write Back and Do Not Invalidate Cache (WBNOINVD)

That's it in terms of new instructions, at least what's enabled by these patches. It's possible there might be some other new instructions supported by Zen 2 that AMD doesn't want to reveal at this time, just like the scheduler cost tables haven't yet been tuned, etc. This patch is basically a starting point so the GCC 9.1 stable update due out in 2019 can at least handle -march=znver2 and that march=native targeting will also work for these next-gen AMD processors.

The first AMD Zen 2 processors expected are 7nm EPYC 2 and we should be hearing more about them in early 2019... Given all the successes we've seen with Threadripper and EPYC 7000 series on Linux already, I am especially excited to see what next-gen EPYC will have in store and how fast it will be.

The patch is currently on gcc-patches but will likely be merged to mainline GCC before the feature freeze goes into effect at the middle of November. The timing of this patch does also reinforce what I reported recently with it looking like AMD has begun their upstreaming / open-sourcing of Zen 2 enablement for the Linux kernel and related components of the open-source toolchain.