AMD plans native 8-core cpu

[Idontcare]

Originally posted by: Arkaign
128-core cluster FTW?

Yes, in my line of work it is very much "FTW".

 

[coldpower27]

Originally posted by: Idontcare

Originally posted by: Extelleron

Originally posted by: Idontcare
http://aceshardware.freeforums...-shanghai-t405-15.html

Nehalem = 246mm^2

Shanghai = 243mm^2

Hans de Vries FTW.

That contradicts what I had seen before regarding Nehalem die sizes... I had previously seen ~270mm^2 estimated.

If that is accurate, then AMD has seen some pretty bad SRAM scaling (63%+ of 65nm size) but good logic scaling (60% of 65nm size).

Checkout Hans post with the embedded graphics to back up the math. Hans is pretty much legend for doing the analysis of CPU die shots.

Per Hans, Nehalem L2$ is 7.1mm2/MB while Shanghai is 7.5mm2/MB...not the end of the world difference but yes Intel has better SRAM density.

Intel really takes off with their L3$ density...5.7mm2/MB for Nehalem versus 7.5mm2/MB for Shanghai.

Yeah it isn't really a fair comparison, were comparing AMD's LV3 caches to Intel's LV2 caches. But with Nehalem vs Shanghai things should be more fair as AMD and Intel will have a large LV3 cache 6MB on Shanghai vs 8MB? on Nehalem..

I was really curious on AMD's L3 density comparison on Barcelona vs Kentsfield LV2.

For now I am expecting 250mm2+/- 10% give or take with Nehalem, we will see.

Shanghai could very well be 230mm2 give or take, 80% of the predecessor core, when you double the cache on the next generation process, 4MB total on Barcelona vs 8MB total on Shanghai is not totally unheard of. I hope Intel keeps the core pair LV2 cache strategy on Nehlaem though.

 

[Idontcare]

Originally posted by: coldpower27

Originally posted by: Idontcare

Originally posted by: Extelleron

Originally posted by: Idontcare
http://aceshardware.freeforums...-shanghai-t405-15.html

Nehalem = 246mm^2

Shanghai = 243mm^2

Hans de Vries FTW.

That contradicts what I had seen before regarding Nehalem die sizes... I had previously seen ~270mm^2 estimated.

If that is accurate, then AMD has seen some pretty bad SRAM scaling (63%+ of 65nm size) but good logic scaling (60% of 65nm size).

Checkout Hans post with the embedded graphics to back up the math. Hans is pretty much legend for doing the analysis of CPU die shots.

Per Hans, Nehalem L2$ is 7.1mm2/MB while Shanghai is 7.5mm2/MB...not the end of the world difference but yes Intel has better SRAM density.

Intel really takes off with their L3$ density...5.7mm2/MB for Nehalem versus 7.5mm2/MB for Shanghai.

Yeah it isn't really a fair comparison, were comparing AMD's LV3 caches to Intel's LV2 caches. But with Nehalem vs Shanghai things should be more fair as AMD and Intel will have a large LV3 cache 6MB on Shanghai vs 8MB? on Nehalem..

I was really curious on AMD's L3 density comparison on Barcelona vs Kentsfield LV2.

For now I am expecting 250mm2+/- 10% give or take with Nehalem, we will see.

Shanghai could very well be 230mm2 give or take, 80% of the predecessor core, when you double the cache on the next generation process, 4MB total on Barcelona vs 8MB total on Shanghai is not totally unheard of. I hope Intel keeps the core pair LV2 cache strategy on Nehlaem though.

Dude! Did you read the f'ing posts you quoted at all!? Seriously that annoys me, probably way to much, but I mean, c'mon, really? :Q

 

[Viditor]

Originally posted by: Idontcare
Dude! Did you read the f'ing posts you quoted at all!? Seriously that annoys me, probably way to much, but I mean, c'mon, really? :Q

To be fair to CP, those numbers (from the quoted post) aren't written in stone at all...
For example, the Nehalem Hans refers to is for 2P and smaller systems only IIRC (learned elsewhere), and has only a 2 channel memory system.
There are other Nehalems for servers that will have a 3 channel mem controller as well, and the die size may be different.

 

[taltamir]

hopefully the would fix the TLB bug before trying to sell quad core phenoms...

 

[Viditor]

Originally posted by: taltamir
hopefully the would fix the TLB bug before trying to sell quad core phenoms...

?
The TLB bug has been fixed
The B3 has been shipping since last month.

 

[Cookie Monster]

Originally posted by: Viditor

Originally posted by: taltamir
hopefully the would fix the TLB bug before trying to sell quad core phenoms...

?
The TLB bug has been fixed
The B3 has been shipping since last month.

So we should be seeing the B3 revisions on the market sometime soon? Have you heard any other bugs mentioning L3/NB speed that could be restricting the agena's performance?

 

[Viditor]

Originally posted by: Cookie Monster

Originally posted by: Viditor

Originally posted by: taltamir
hopefully the would fix the TLB bug before trying to sell quad core phenoms...

?
The TLB bug has been fixed
The B3 has been shipping since last month.

So we should be seeing the B3 revisions on the market sometime soon? Have you heard any other bugs mentioning L3/NB speed that could be restricting the agena's performance?

Haven't heard of other bugs...
Don't know when they will show up in the channel, but the new Barcelona servers are due out in the first week of April (after building and testing of the systems is done).

 

[Dadofamunky]

Originally posted by: GuitarDaddy
This "Core Wars" thing is getting pretty ridiculous, it's great for the server market but for desktop usage Intel and AMD will both have 8-core CPU's out long before any normal software even takes advantage of 4-cores

Kinda sad: (for those like me who don't do folding or video encoding. I have a strong dual core CPU running 3+ghz and I see nothing worthy of an upgrade in the next year or so.

I agree with this. I can't see any need for me to have more than two high-performance cores for quite some time. Eventually I'll probably get a 45nm quad-core just to stay reasonably current. Nothing I do requires more than that, and I heavily use the very latest Adobe apps. Eight cores? Good for things like network processing or deep packet inspection, but way outpacing the consumer/enthusiast desktop market. Exciting nonetheless, but it's gonna be a tough sell for a lot of people who aren't OCing or upgrading freaks. Anyone doing folding or encoding or whatever that can support 4+ threads are a tiny minority. Companies can't make profit off that market alone. So it all comes down to marketing. You NEED this! (Even though nothing you do USES it. But we won't tell you that. ) Now in my field (networking), I think it's a GREAT thing. It's also outstanding for server farms. For me, eh, not so much.

I didn't know that Supreme Commander supported four threads. That's pretty darn cool. They've shown that it can be done.

Let the 45nm wars begin!

The software jocks really need to get BUSY!

 

[myocardia]

Originally posted by: Dadofamunky
I didn't know that Supreme Commander supported four threads. That's pretty darn cool. They've shown that it can be done.

Let the 45nm wars begin!

The software jocks really need to get BUSY!

There is more than one game that supports quad cores, to varying degrees of success, of course. Then again, the "software jocks" have never supported anything until there was an installed user base that could actually benefit from their work.

 

[dmens]

Originally posted by: Viditor
To be fair to CP, those numbers (from the quoted post) aren't written in stone at all...
For example, the Nehalem Hans refers to is for 2P and smaller systems only IIRC (learned elsewhere), and has only a 2 channel memory system.
There are other Nehalems for servers that will have a 3 channel mem controller as well, and the die size may be different.

Hans is wrong, that die has the three DDR channels.

 

[Phynaz]

Originally posted by: Viditor

Originally posted by: taltamir
hopefully the would fix the TLB bug before trying to sell quad core phenoms...

?
The TLB bug has been fixed
The B3 has been samplng since last month.

Fixed that for you.

 

[batmang]

I'll be their with my Spider2 platform.

 

[Viditor]

Originally posted by: dmens

Originally posted by: Viditor
To be fair to CP, those numbers (from the quoted post) aren't written in stone at all...
For example, the Nehalem Hans refers to is for 2P and smaller systems only IIRC (learned elsewhere), and has only a 2 channel memory system.
There are other Nehalems for servers that will have a 3 channel mem controller as well, and the die size may be different.

Hans is wrong, that die has the three DDR channels.

Good to know...I must admit that I did a magnified comparison between the die that Hans has and the one in Intel's press kit (which is labeled 3 channel), and I couldn't find any difference at all.

My understanding is that the 2P version of Nehalem will have only a 2 channel controller...do you know if this is true?