Question AMD Phoenix/Zen 4 APU Speculation and Discussion

[uzzi38]

I can finally make this thread.

https://twitter.com/x/status/1519669375283957760

Phoenix is indeed RDNA3. My advice to everyone: treat the old APU rumours as being out of date.

 

[Shivansps]

Zen 4 chiplet is 66.3mm² design area.
Zen 4C chiplet is 72.7mm² design area.

The Zen 4C CCD is just ~10% larger than Zen 4. To achieve this, everything is tightly packed to improve density. Some features like the TSVs for 3D cache are gone. If we ignore the L2, the core shrank by about 44%. Doubling the core count meant double the L2 as well, but that was compensated by less L3 per core.

Its definately impressive for something AMD itseft says its not an "small core", but something is off here, why use Zen4 for APUs at all then? And specially for Phoenix 2 they could have gotten away with just Zen4C and make it smaller.

 

[jpiniero]

Its definately impressive for something AMD itseft says its not an "small core", but something is off here, why use Zen4 for APUs at all then? And specially for Phoenix 2 they could have gotten away with just Zen4C and make it smaller.

Single Thread. Without any Z4 cores it would get killed by Raptor Lake because of the clock speed gap.

 

[Markfw]

Single Thread. Without any Z4 cores it would get killed by Raptor Lake because of the clock speed gap.

Zen4c is the same as Zen 4 except a little less cache, and a little less speed. Raptor lake has less P-cores, and the e-cores are junk compared to Zen4c.

I doubt that they would lose.

 

[jpiniero]

and a little less speed.

Is 35% a little less to you? (Boost of 5 vs 3.7)

 

[gdansk]

Is 35% a little less to you? (5 vs 3.7)

How much less is it than a Zen 4 core when running a MT workload?
Does anyone know the 8700G/8600G all core boost vs 8500G yet?

But yes, a Zen 4C only design is a bad idea for consumer devices. It's fine for servers.

 

[jpiniero]

How much less is it than a Zen 4 core when running a MT workload?
Does anyone know the 8700G/8600G all core boost vs 8500G yet?

Official base clock on the 8500G is 4.1 on Z4 vs 3.2 on Z4c.

 

[gdansk]

Official base clock on the 8500G is 4.1 on Z4 vs 3.2 on Z4c.

Base clocks are not very typical, at least based on other 65W Zen 4 parts I've tested. A 7700 typically does >4.8 GHz on all cores in Cinebench, for example, despite a 3.8GHz base clock.

So it is possible the difference between Zen 4C and 4 will be even larger in the real world for Phoenix 2.

 

[Shivansps]

We do not know yet if the clocks on Zen4C is a artificial limit to keep power low or if they really cant clock north of 4Ghz.

 

[FlameTail]

We do not know yet if the clocks on Zen4C is a artificial limit to keep power low or if they really cant clock north of 4Ghz.

In that case, we will need overclockers to test out how high it can go?

 

[SteinFG]

In that case, we will need overclockers to test out how high it can go?

The news outlet that originally (on november 5th) leaked 8500G/8300G/5600GT/5500GT/5700 processors, said that Phoenix2 chips (8500G/8300G) only have PBO settings, so pretty much locked. link

 

[eek2121]

Base clocks are not very typical, at least based on other 65W Zen 4 parts I've tested. A 7700 typically does >4.8 GHz on all cores in Cinebench, for example, despite a 3.8GHz base clock.

So it is possible the difference between Zen 4C and 4 will be even larger in the real world for Phoenix 2.

Try Prime95 small FFTs with AVX-512.

We do not know yet if the clocks on Zen4C is a artificial limit to keep power low or if they really cant clock north of 4Ghz.

I suspect they are very close to the “limit”. If AMD could get Zen4C over 4ghz they would’ve done so with Genoa or a midrange part.

 

[moinmoin]

We do not know yet if the clocks on Zen4C is a artificial limit to keep power low or if they really cant clock north of 4Ghz.

It's likely not an artificial limit. Zen 4 cores are huge compared to Zen 3 despite the node change and saw a much bigger increase in transistor count than the added capability warranted. Size wise Zen 4c cores are more along the line of what should have been expected from a "normal" Zen 4 core. What happened is that for Zen 4 a lot of transistors were invested to reach the high frequencies it does. Conversely this is how Zen 4c cores could save so much area, giving up the transistors again that previously made the high frequencies possible.

 

[Shivansps]

The news outlet that originally (on november 5th) leaked 8500G/8300G/5600GT/5500GT/5700 processors, said that Phoenix2 chips (8500G/8300G) only have PBO settings, so pretty much locked. link

I was gona say thats probably a beta firmware issue as they would not dare to launch a locked Ryzen 5, but it is now very clear to me that no one will care if they do.

 

[igor_kavinski]

giving up the transistors again that previously made the high frequencies possible.

What do these transistors actually do to make the high frequencies possible?

 

[igor_kavinski]

We do not know yet if the clocks on Zen4C is a artificial limit to keep power low or if they really cant clock north of 4Ghz.

Would be cool if a slight dot from a pencil unlocks it

Wanna see those fireworks go in a Youtube video from GN or heck, even LTT.

 

[SteinFG]

What do these transistors actually do to make the high frequencies possible?

Dark Silicon basically. there're no transistors in places where they could have beed placed

 

[naukkis]

What do these transistors actually do to make the high frequencies possible?

Transistor needs to offer enough current amplification to be able to drive chain of other transistors. That amplification speed can be increased with using more and/or bigger transistors in complex schemes. for simplified explain think replacing small transistor driving 4 other transistors with tree transistors, one driving two which both of drives two of those 4 original transistors. With those additional transistors circuit capacitance can be reduced and max operating speed increased - though with increased power.

 

[Abwx]

What do these transistors actually do to make the high frequencies possible?

A transistor has a parisitic capacitance that goes from the active output back to the input, even if the transistor is very fast this capacitance, despite being of low value, is a limiting factor because it introduce a negative feedback that considerably reduce the speed, the higher the frequency the more the negative feedback because the impedance (equivalent resistance) of a capacitor is Z = 1/2pi.FC, F the frequency and C the capacitance.

So they use two transistors in serial with one being always switched on and wich is in serial with the switching transistor, this way the output/input capacitance is grounded on a dynamic point of view, that is, it insulate the input from the output, theorically this improve speed by 30%, surely that Zen4c FI doesnt use this configuration, hence a lower max frequency but a much lower transistor count.

 

[Hitman928]

A transistor has a parisitic capacitance that goes from the active output back to the input, even if the transistor is very fast this capacitance, despite being of low value, is a limiting factor because it introduce a negative feedback that considerably reduce the speed, the higher the frequency the more the negative feedback because the impedance (equivalent resistance) of a capacitor is Z = 1/2pi.FC, F the frequency and C the capacitance.

So they use two transistors in serial with one being always switched on and wich is in serial with the switching transistor, this way the output/input capacitance is grounded on a dynamic point of view, that is, it insulate the input from the output, theorically this improve speed by 30%, surely that Zen4c FI doesnt use this configuration, hence a lower max frequency but a much lower transistor count.

We've had this debate before, but you really should put that this is your own working theory and not an actual industry used design principle. The explanation @naukkis gave is much closer to what is actually done in digital design.

 

[Abwx]

We've had this debate before, but you really should put that this is your own working theory and not an actual industry used design principle. The explanation @naukkis gave is much closer to what is actually done in digital design.

No, his explanation would amount to higher power comsumption at a same frequency, while what i m explaining require the same power comsumption at a given frequency, that s all the difference.

You have some knowledge, undoubtly, but you dont understand what it is about here, that s because you think that a switching transistor is not an analog component, hence your flawed assumptions and insistance because you dont understand the matter.

For the time all you need to know is that for finfets, contrary to planar transistors, the limiting factor for speed is the miller effect (not the current capability) within the transistors, that s documented, and what i m talking about is how to neuter this effect.

FinFET: The Miller’s Tale - Semiwiki

In Chaucer’s Canterbury Tales, the second of the tales told by the pilgrims is The Miller’s Tale. Since this is a family blog, I’ll leave you to research the tale yourself. But FinFETs hide another Miller’s Tale, due to Miller capacitance, sometimes called the Miller effect. This is significant...

semiwiki.com

Is that good enough to help you understand.?..You could have googled the thing and got out of your erroneous insistance and non sense, basically here i m doing your homework.

 

[Hitman928]

No, his explanation would amount to higher power comsumption at a same frequency, while what i m explaining require the same power comsumption at a given frequency, that s all the difference.

You have some knowledge, undoubtly, but you dont understand what it is about here, that s because you think that a switching transistor is not an analog component, hence your flawed assumptions and insistance because you dont understand the matter.

For the time all you need to know is that for finfets, contrary to planar transistors, the limiting factor for speed is the miller effect (not the current capability) within the transistors, that s documented, and what i m talking about is how to neuter this effect.

FinFET: The Miller’s Tale - Semiwiki

In Chaucer’s Canterbury Tales, the second of the tales told by the pilgrims is The Miller’s Tale. Since this is a family blog, I’ll leave you to research the tale yourself. But FinFETs hide another Miller’s Tale, due to Miller capacitance, sometimes called the Miller effect. This is significant...

semiwiki.com

Is that good enough to help you understand.?..You could have googled the thing and got out of your erroneous insistance and non sense.

I have several years of university education on electrical engineering and circuit design, I don't need to google it. The digital domain is simply the analog domain with a bunch of assumptions which allows you to greatly simplify the equations and design work on a per transistor basis. The Miller effect or Miller cap is real and is extremely well understood in circuit design, you are not shedding any new light here for people who do circuit design for a living. Where my critique of your posting comes is in how you say the Miller cap is handled in digital design, which is simply not accurate.

 

[Abwx]

I have several years of university education on electrical engineering and circuit design, I don't need to google it. The digital domain is simply the analog domain with a bunch of assumptions which allows you to greatly simplify the equations and design work on a per transistor basis. The Miller effect or Miller cap is real and is extremely well understood in circuit design, you are not shedding any new light here for people who do circuit design for a living. Where my critique of your posting comes is in how you say the Miller cap is handled in digital design, which is simply not accurate.

Read the article rather than displaying your credentials, it s explicitely stated that this effect is the limiting factor for finfets speed, i too can as well display what i know about LTIs, aka, linear time invariant systems, that wouldnt be a prove that i really understand electronic design in its details.

Yes you know what is this effect, but you were unaware that it s a problem and limiting factor when it comes to CPUs, you thought that it was an issue only with usual analog circuitries like opamps, wich by the way i m perfectly capable to design.

 

[Hitman928]

Read the article rather than displaying your credentials, it s explicitely stated that this effect is the limiting factor for finfets speed, i too can as well display what i know about LTIs, aka, linear time invariant systems, that wouldnt be a prove that i really understand electronic design in its details.

Yes you know what is this effect, but you were unaware that it s a problem and limiting factor when it comes to CPUs, you thought that it was an issue only with usual analog circuitries like opamps, wich by the way i m perfectly capable to design.

No, just no, on every point.

I'm not getting into another back and forth with you because it's a waste of time. I just wanted to basically flag your post as fan fiction so others who don't know better get the wrong idea about how digital design works. Feel free to keep posting but I won't be dragged into another inane discussion on this matter.

 

[Abwx]

No, just no, on every point.

I'm not getting into another back and forth with you because it's a waste of time. I just wanted to basically flag your post as fan fiction so others who don't know better get the wrong idea about how digital design works. Feel free to keep posting but I won't be dragged into another inane discussion on this matter.

You are just eluding the debate because you are slowly realising that you are in the wrong, rather than learning you prefer to close your eyes.

For those who have a basic knowledge of transistors i ll explain Semiwiki schematic :

Both amplifying devices here are just fet transistors, and they are in serial.

The first transistor input is its gate, and its output is its drain, its source is connected to a supply voltage rail.

The drain of the first transistor (its output) drive the source of the second transistor, hence the source of the second transistor is used as its input, and its drain is the output OUT, its gate is connected to a voltage rail and the transistor is always on, and hence its own miller capacitance is grounded, only the first transistor is switched on and off.

The source of the second transistor is a very low impedance node, hence the miller capacitance that goes from gate to drain of the first transistor is grounded due to the low input impedance of the second transistor, that what is displayed in this schematic.

When the first transistor is switched on or off there s only a current variation flowing from its drain to its source and no significant dv/dt occur from its drain (its output) to its gate (its input), that is, the miller capacitance of the first (and only switching transistor here) see no dv/dt at its ends and is hence neutered.

 

[Hitman928]

You are just eluding the debate because you are slowly realising that you are in the wrong, rather than learning you prefer to close your eyes.

LOL. Whatever helps you sleep better at night smh.