AMD Opteron Spec Scores:

[Rand]

Courtesy of the Register, as told by AMD's John Crank....

On debute the AMD Opteron will post a SPECint of 1202 and SPECfp of 1170.

Pretty impressive given AMD processors typical underperform in Spec realtive to real world desktop application performance.
Spec will of course be considerably more important for the Opteron then it has for any of their past processors given the intended market for it.

Register linky

According to David Wang of RWT the Spec scores were from an Opteron running at 2Ghz with registered PC2700 DDR SDRAM memory. Tests were done using Intel compilers, in 32 bit mode. Fred Webber claims that with a 64 bit clean compiler, the Opteron should see upwards of 20% better performance on some code due to the extra registers available in AMD's X86-64 implementation. additional registers


Hard to guesstimate ClawHammer performance based on the above, but as a wild guess I'd expect somewhere around 1080Spec Int, and 940 SpecFP.
Nicely balanced between Integer/FP Spec performance.
Intel should be pushing out the Gallatin sometime around when the Opteron is released.

FWIW, for those that arent aware, the Gallatin is the large cache Xeon's, ie. $ 4K/processor.

 

[Tab]

What speed do you think the FSB and Cache will the Opteron willl have? I can't wait until we start seeing Hammer mobo's and the such. I love my life, it revolves around computers I hope the Hammer has some comparable FSB Speeds to the P4.

 

[Inept]

The Hammer does not have an FSB because its memory controller is integrated. As for Cache, I don't know.

 

[Bluga]

wow sweet.

 

[Chadder007]

Originally posted by: Inept
The Hammer does not have an FSB because its memory controller is integrated. As for Cache, I don't know.

It has to have a FSB to clock man..... 0 FSB x 2000 clock integer = 0

 

[Inept]

Nope. FSB = CPU to Memory interface. As it just so happens, we use a multiple of it to generate the internal clock for our processors and the clocks for our perhiperal busses. Now that the memory controller will be integrated into the chip, the FSB as we know it is gone. There will be something there, of course, since the processor, PCI BUS, etc. need clocks.

 

[odog]

their is a FSB here, but it's not external. it's also not something seen before on a grand scale.

 

[MadRat]

The Hammer fsb = 800MHz HDT x 16-bit pathway x 2-directional = 400MHz equivalent

 

[odog]

what he said.

 

[Rand]

Inept is correct, technically speaking there is no FSB on the Hammer.
As a direct translation the FSB is the connection between the microprocessor and the memory controller.
On the Hammer' there is no connection between the two... the memory controller is directly on the die of the microprocessor.

Essentailly they are together, therefore the FSB would be the full clockspeed of the processor, as they are together.

 

[Rand]

In answer to Tabb regarding cache-
Opteron: 64kb L1-D , 64 kb L1-I and 1-2MB L2 cache
ClawHammer: 64K L1-D, 64 kb L1-I and 256KB-512KB L2 Cache.

All on-die running at the full clockspeed of the processor.

 

[JeremiahTheGreat]

sweeeeet!

now all we have to do is wait.. maybe they'll even put in QDR support in ? same ram socket..

 

[BFG10K]

It'll be interesting to see how it performs in the real world.

 

[Rand]

Originally posted by: JeremiahTheGreat
sweeeeet!

now all we have to do is wait.. maybe they'll even put in QDR support in ? same ram socket..

Initially it's supposed to support PC1600/2100/2700 DDR, with DDR-II support being added in 2004.

 

[Rand]

Further info from RWT insinuates the test was done on a 1MB L2 cache Opteron, meaning this is likley from the "low-end" Opteron. I wonder how much the extra 1MB cache would help out the 2MB Opteron?

 

[andreasl]

Another interesting thing is that the scores are with 32-bit Intel compilers. That might say something about the speed of the x86-64 compilers at present

 

[Dulanic]

The main thing I wonder is how overclocking the RAM will work.. or if you can. I really hope its possible, it would seem the memory core on die has its own clock since nothing else runs at the same speed as the ram now... which means maybe you can set the RAM to any speed.... which would be awsome... always could overclock your ram to top speed!

 

[majewski9]

wow 1 and 2 meg versions! AMD is looking more and more competetive! The opteron was originally not going to be released @ 2ghz. Rather it was suppossed to be launched at a mere 1.6ghz. Could this mean that the Opteron will be released at a much higher clock speed? Id also like to point that the 2ghz opteron had a clear margin of victory against the 2.8ghz p4 and the AthlonXP 2800. Not bad!

 

[Athlon4all]

Yes, I did notice this. Impressive, I am wondering however is it Dual Channel DDR or Single Channel. Very Impressive.

 

[Dulanic]

 

[Rand]

Originally posted by: Athlon4all
Yes, I did notice this. Impressive, I am wondering however is it Dual Channel DDR or Single Channel. Very Impressive.

SledgeHammer/Opteron is DualChannel DDR, the desktop ClawHammer is relegated to single channel DDR.

 

[cliftonite]

What will the SledgeHammer/Opteron and the clawhammer retail for?

 

[socketman]

Here is some interesting info.

He cited two popular benchmarks as "misleading," SPECfp and SPECint, which are used to measure floating point and integer performance, respectively.
The problem, he said, is that the larger on-die memory caches on some chips, such as Itanium 2's 3MB cache, skew the results since they can accommodate the entire benchmark program, and thus don't have to off-die to access memory, which is unrealistic.
"When a customer uses the system on real-life applications, they have to access off-chip memory, they have to access the network and peripherals," he said. "They are not going to get the kind of performance they expected from the SPEC benchmarks."

Source:http://www.extremetech.com/article2/0,3973,285242,00.asp

Article on Spec benches: http://www.arstechnica.com/cpu/2q99/benchmarking-1.html

Here is a link to some Itanium benches:http://www.geek.com/news/geeknews/2002Jul/bch20020703015249.htm

 

[Accord99]

Originally posted by: socketman
Here is some interesting info.

He cited two popular benchmarks as "misleading," SPECfp and SPECint, which are used to measure floating point and integer performance, respectively.
The problem, he said, is that the larger on-die memory caches on some chips, such as Itanium 2's 3MB cache, skew the results since they can accommodate the entire benchmark program, and thus don't have to off-die to access memory, which is unrealistic.
"When a customer uses the system on real-life applications, they have to access off-chip memory, they have to access the network and peripherals," he said. "They are not going to get the kind of performance they expected from the SPEC benchmarks."

Source:http://www.extremetech.com/article2/0,3973,285242,00.asp

SPEC is the most used and most important cross-platform benchmark available today and influences greatly the design of modern high performance CPUs. As well, looking at the memory footprint of the subtests, only one test would fit within the Itanium2's L2 cache. Most have footprints in 100+ MB range. Of course, a Sun guy would dismiss SPEC scores since they clearly highlight the performance defiencies of Sun chips in single or small-number cpu configurations, but there are other SPEC tests to measure scalability, the area that they excel in.

 

[Bovinicus]

The Opteron scores look to be very promising compared to the Athlon MP. As long as the Clawhammer's scores aren't too much lower than that we should see some seriously competitive performance from this platform. The idea of an integrated memory controller is an excellent one. Memory latency is of great importance in consumer applications, and an integrated memory controller should mean very low memory latency. Of course, speculation does no good. The only way to see how it benchmarks is to wait for the reviews.