AMD: Moore's Law's end is near

[aigomorla]

The process node label is just that, a label. It is not intended to be a numerical reference to anything with physical dimensionality.

We already do this with gate oxides, have for more than 15yrs. We call it "EOT" for effective xide thickness. We measure the electrical characteristics of the oxide and then assign a fictious value to it for its thickness in terms of how thin the oxide would be if it were made from traditional silicon dioxide.

So you get silly numbers like "3Å EOT" which defies physics as silicon dioxide cannot physically be any thinner than 7Å, and so on.

isnt this what ive been saying again for the longest time?
on the standard silicon die... were about at the EOL.

I remember guys at intel telling me. Moore's law is gonna be flatlined soon, because process node technology can not keep up with the law itself.
Hence why they were playing with other mediums like super conductive carbon....

Although i havent heard anymore more about these... as i havent been in the game as hardcore as i used to due to the stagnate nature of the cpu's lately.

IDC u recall when i got laughed at saying moore's law is nowhere gone for a long ass time....

You wrote that the non-electrical parameters in a node shrink are nearly useless for anything but reducing costs. How should I have interpreted that?

thats exactly how u should interpret it.
Intel has never created a monster sized CPU just to add more nodes on there existent node size without a die shrinkage.
You think just increasing a die doesnt lead to other can of worms?

We can have 100nm monolith dies with spams and spams of IVY cores but intel wont due it. why?
Again when you make a Die that big.. it introduces other problems on equal sizes.

 

[Idontcare]

IDC: I understand the technicals. I don't understand the marketing.

Companies usually cheat to make themselves look better (Exhibit A: Bulldozer cores.) So I could see a company saying their chip is 0.35 when it's really only 0.40.

But I would think that if the actual minimum feature size was 0.30, the marketing people would be falling over themselves to call it a "0.30 chip".

I was just surprised by your graph, because I assumed that right now the whole issue is "they say they've shrunk it down to X, but they've only shrunk it down to 1.2X" (or whatever).

At the time there was much less marketing surrounding node labels than there is today.

Nowadays node labels are advertised because it has been tied into brand value, and from there it goes to stock value.

There was a level of professional understanding as to what the node label meant and why it was used. That all broke down after the dot-com crash as businesses scrambled to figure out how they could entice shareholders to value the stock at prices that resembled the pre-2000 crash.

Consider for a moment why Intel would bother spending the millions it spent in terms of salaries and project time just in creating the publicity documents (PR and videos) to hype the existence of its 22nm 3D xtor tech. That wasn't expensed for the benefit of the CPU consumer, it was for the benefit of the INTC owner.

 

[pm]

That is not what I wrote.

But even in your example (GPUs) you are not correct as the xtor density of GPUs is not that of the allowed maximum for the node (on any node).

Before Intel's 22nm 3D xtors, xtors are/were two-dimensional. Gate length captures only one of those two dimensions, the second dimension (referred to as the gate width) is many times larger than the length and in most circuits is nowhere near the minimum allowed by the process node.

Sram is about the only time you see circuits physically laid out in which the xtor density actually approaches the maximum allowed by the node's design rules. Everything else is physically larger for reasons that run counter to your stated post.

But all of that is irrelevant in terms of my post above to which you were responding as you did not read what I wrote. If you simply physically scale a transistor without scaling the electrical characteristics in kind then you gain nothing.

If you want to just tread water (same clockspeed, same power usage, etc) while making the chip smaller in area then you must increase drive current and reduce leakage parameters commensurate to the dimensional scaling.

If you don't do any of that (which is what I was discussing) then physically shrinking the chip actually hurts the chip's electrical parametrics.

And you know that already, even if you didn't realize you did, because the transistor density of a CPU is significantly less than that of a GPU which in turn is significantly less than that of the highest density layouts allowed for sram on the same node. There is a reason why the CPU is not physically shrunk to the same density as the sram circuits even though the node's design rules can accommodate it.

If the SB design engineers could have improved on SB by using physically smaller transistors (without improved electrical parametrics) then they would have, they were available but went unused. The transistor widths used in the logic circuits of my 2600k cannot be narrower if the chip was to operate at its target clockspeed, power consumption, and desired operational lifetime (reliability). It had to be as big as it is for good reasons.

We've debated this before, Idontcare, and you know more about process technology than I do (which isn't flattery, just the plain truth) so always agree with you in the end, but what you are saying doesn't match up with what I see at Intel. I see transistor density continuing to improve from generation to generation regardless of the library cell you look at - the wiring pitches are tighter, contact placement is tighter, transistors are smaller. I agree with you that lots of physical parameters - like tox - are not scaling as they should due to physics restrictions, but from a higher level view of a block of logic, I still see designs getting much more compact and physically smaller. And I've recently been doing contactless probing of a future server product and I can even see visually that the transistors are all smaller.

It also doesn't match up with what Mark Bohr says internally and externally about process improvements - he says that they need to low cost. If wafer cost is rising - and we all can see that it is - then transistor density simply must improve to offset this rising wafer cost in order to fulfill this rule..

Here's a quote:
http://www.eetimes.com/electronics-news/4403075/IBM--Intel-face-off-in-22-nm-process-at-IEDM

“Cost per wafer has always gone up marginally each generation, somewhat more so in recent generations, but that’s more than offset by increases in transistor density so that the cost per transistor continues to go down at 14 nm,” Bohr said.

I am currently working on a 14nm design and density is much better than it was at 22nm - and this is CPU register cell density, not an SRAM.

 

[Homeles]

IDC was definitely not saying that density isn't improving...

 

[pm]

IDC was definitely not saying that density isn't improving...

Hmmm... then I misread him. I need to prowl through the thread more carefully.

 

[Exophase]

If you want to assume I don't know what I am talking about, and that you are the expert here when it comes to process node development, then I will neither argue with you nor stand in your way.

You seem quite intent on debunking what I write, but to do that you must first misinterpret what I am writing and build yourself a few strawmen to then tear down. Have at it, I have nothing to lose if you wish to remain ignorant.

I don't pretend to know anywhere near what you do on process development. But that doesn't mean you know everything about the designs implemented on those processes.

I'm not getting the straw man here. I don't see any ambiguity or room for misinterpretation in your comment that if you don't improve the electrical performance of transistors but only enable higher density you gain nothing (with a side note that it decreases costs). That's just not true. There are tons of ways in which you can use more transistors to improve the efficiency of a design even if the transistors themselves aren't faster or lower power.

This can be true even if the electrical characteristics get worse like you're saying a naive physical shrink would entail. Determining where this trade-off point becomes reasonable for discussion is a complex and highly dependent on what you're designing.

 

[Homeles]

Hmmm... then I misread him. I need to prowl through the thread more carefully.

He's saying that increasing density is meaningless or counter-productive if you aren't improving the electrical characteristics at the same time.

Ivy Bridge is definitely smaller and denser than Sandy Bridge. Surely Idontcare isn't claiming the contrary.

 

[pm]

He's saying that increasing density is meaningless or counter-productive if you aren't improving the electrical characteristics at the same time.

Ivy Bridge is definitely smaller and denser than Sandy Bridge. Surely Idontcare isn't claiming the contrary.

Well, no, I would say that lower manufacturing costs are the primary driver of process improvements... improved electrical characteristics, if there are any, are just a nice side-benefit. I mean you would prefer things don't get worse, but clearly there's lots of electrical characteristics that do get worse as you scale (Ioff, interconnect R & C, are two that jump to mind). Even if something fundamental like idsat didn't scale and remained a constant from one generation to the next, it would still be worth pursuing the next node just due to manufacturing cost improvements.

I would argue the reverse, that without manufacturing cost improvements, it would be hard to justify scaling just for slightly improved electrical characteristics.

 

[Hulk]

There are tons of ways in which you can use more transistors to improve the efficiency of a design even if the transistors themselves aren't faster or lower power.

Indeed. Every tick-tock shows increased IPC at the using the same process. But then again a tick-tock-tock cycle would surely make meaningful IPC in the 2nd tock increasingly difficult. And not nearly as cost effective since the die size would now actually be growing. Either prices would have to rise or profits fall. Not a good situation when compared to the current paradigm of higher performance, smaller dies, greater profit, and static cost for the consumer from generation-to-generation with the "tick."

 

[bshole]

I built a computer for gaming in 1997. Three years later I built a new computer because the old one was simply obsolete, the difference in power and capability was staggering. I built computer for gaming in 2006, I built a computer to replace just this month. While the new computer is clearly superior than the old machine, the old machine can do everything the new can do, albeit noticeably slower and at lower graphics quality (for gaming). It just doesn't seem like we are advancing at nearly the rate we were pre-2000.

 

[Exophase]

Indeed. Every tick-tock shows increased IPC at the using the same process. But then again a tick-tock-tock cycle would surely make meaningful IPC in the 2nd tock increasingly difficult. And not nearly as cost effective since the die size would now actually be growing. Either prices would have to rise or profits fall. Not a good situation when compared to the current paradigm of higher performance, smaller dies, greater profit, and static cost for the consumer from generation-to-generation with the "tick."

I agree with this. New processing nodes are expensive and have to be useful enough for a wide variety of applications to really be justifiable. I wouldn't argue against Intel's approach at all.

What I'm stressing is I don't see how an absolute argument can be made that smaller transistors that don't improve electrical parametrics can never improve a design (beyond making it cheaper). Even if the individual transistors are slower and/or more power hungry. If you have a design that can perform nearly as well with 2x the transistors and 1/2 the clock speed then there could still be a big efficiency win even if the power consumption/MHz of the transistors is higher. Finding out what will win doesn't sound straightforward at all.

I'm curious how the electrical characteristics changed between say, Samsung's 32nm and 28nm processes.

 

[aigomorla]

He's saying that increasing density is meaningless or counter-productive if you aren't improving the electrical characteristics at the same time.

Ivy Bridge is definitely smaller and denser than Sandy Bridge. Surely Idontcare isn't claiming the contrary.

+1...

he's saying increasing density without reductions in power to said nodes isnt worth an advancement.

and to intel that is correct.

Intel has played with the monolithic dies...
Ive seen them... Ive even seen pictures of multi die nodes which were big monoliths..

However who wants a big ass cray with a working evaporation cooling waterfall like how they were made?

Even big companies are moving away from the power hungry servers to more green ones...
power hungry dies are not profitable.. and as i said, they bring in more problems then benefits.

Also correct me if im wrong or not..
but IDC doesnt the larger dies also leak more power naturally?

 

[Idontcare]

We've debated this before, Idontcare, and you know more about process technology than I do (which isn't flattery, just the plain truth) so always agree with you in the end, but what you are saying doesn't match up with what I see at Intel. I see transistor density continuing to improve from generation to generation regardless of the library cell you look at - the wiring pitches are tighter, contact placement is tighter, transistors are smaller. I agree with you that lots of physical parameters - like tox - are not scaling as they should due to physics restrictions, but from a higher level view of a block of logic, I still see designs getting much more compact and physically smaller. And I've recently been doing contactless probing of a future server product and I can even see visually that the transistors are all smaller.

It also doesn't match up with what Mark Bohr says internally and externally about process improvements - he says that they need to low cost. If wafer cost is rising - and we all can see that it is - then transistor density simply must improve to offset this rising wafer cost in order to fulfill this rule..

Here's a quote:
http://www.eetimes.com/electronics-news/4403075/IBM--Intel-face-off-in-22-nm-process-at-IEDM



I am currently working on a 14nm design and density is much better than it was at 22nm - and this is CPU register cell density, not an SRAM.

Physical scaling is very much alive, and will be for at least another 10yrs and maybe even longer still.

We can see our way down to 1.2nm with what we know of existing physics and chemistry.

Physical scaling is not about "can it be done?", that is the trivial solution because of course it can be done. But the challenge is "can it be done economically?"...and that is why it will take us 20yrs before we get to 1.2nm length-scales.

We will spend those 20yrs figuring out how to do what we can already do, but do it cheaply enough that profits can be made in doing it.

Below 1.2nm is the tough stuff, we require new physics to manipulate computing below that level if we intend to go there with the existing periodic table and chemistry know-how.

So, yeah, if I somehow convinced you (or anyone else) that I was trying to argue that scaling is dead then I miscommunicated somewhere along the way (my bad).

 

[Idontcare]

What I'm stressing is I don't see how an absolute argument can be made that smaller transistors that don't improve electrical parametrics can never improve a design (beyond making it cheaper). Even if the individual transistors are slower and/or more power hungry. If you have a design that can perform nearly as well with 2x the transistors and 1/2 the clock speed then there could still be a big efficiency win even if the power consumption/MHz of the transistors is higher. Finding out what will win doesn't sound straightforward at all.

Why does a GPU use xtors that are larger than the minimum allowed by the design rule?

If what you propose were true then they would never do that. They would always use the smallest possible xtor for a given node and create dense slow circuits (but cram more of them onto the same die).

In your mind the design engineers would always opt to use the absolute smallest xtors allowed by the design rules, and then add more xtrs to flesh out the chip.

But that isn't what happens in reality, ever, and there are good reasons why. A product's performance is rarely optimized on the basis of xtor count, it is optimized on the basis of the electrical parameters of the xtors.

The smallest allowed transistor layouts for a given node's design rules rarely go used in the layout of an IC. They will be used in sram arrays, but even in those arrays they aren't used 100% of the time.

My point in referring to xtor density is because the answer to your own quandary is presently available on the market. Every IC you come in contact with could have been designed to use denser circuits on the same exact node, and then used more xtors to do all the extra performance-enhancing stuff you think they would do if they had smaller transistors. But that isn't what happened. Instead the design guys use larger transistors, wider transistors, throughout the design because there is a tradeoff between performance, die-size, and xtor size for a given portfolio of electrical parameters.

The design guys already have smaller transistors available to them at every node, they don't use them in wholesale because it doesn't produce a superior product. They would use the smallest xtors allowed if they had superior electrical properties over the larger ones though, and that is what a new node delivers.

 

[Exophase]

I'm not seeing the argument of a design not using the densest possible transistors as automatically equivalent to a process shrink that improves density without improvement to electrical characteristics (and worse performance at smaller physical sizes) being universally useless.

To even begin evaluating this you'd first have to quantify how much lower performing this hypothetical physical-shrink only process is, and what a shrink that only improves physical size w/o electrical parametrics fully entails. If you're saying that this hypothetical shrink is nothing more than restricting usage to smaller transistor types already available then yes, I guess I'd have to agree. But just because the smallest transistors plus densest possible layouts aren't used everywhere doesn't mean they're only used in SRAM, and it doesn't mean that if those were expanded to include a smaller option that it couldn't be useful for parts of the circuit, potentially even at the expense of performance of those smaller transistors. Even the ability to add a lot more SRAM is useful for perf/W, if you want to limit it to that.

 

[Idontcare]

Even in sram the smallest allowed xtors aren't routinely used. Intel's L1$ always uses larger xtors than their L3$, even though they could have a larger L1$ (bit-total wise) if they did use the slower/denser L3$ sram in their L1$ design.

The trade-offs are all determined and calculated during the development phase of the node itself. It is one of the guiding aspects of node development, otherwise imbalances would be introduced in terms of spending too much R&D effort optimizing one parameter at the expense of not improving enough on another parameter.

Maybe what is missing here is an understanding of how xtor dimensions factor into the design of a circuit, why both dimensions (gate length and gate width) are variables to be optimized during design and are not just a fixed minimum value set by a given node?

 

[Idontcare]

If you want to assume I don't know what I am talking about, and that you are the expert here when it comes to process node development, then I will neither argue with you nor stand in your way.

You seem quite intent on debunking what I write, but to do that you must first misinterpret what I am writing and build yourself a few strawmen to then tear down. Have at it, I have nothing to lose if you wish to remain ignorant.

Just wanted to take a public moment here to reflect on this post of mine and offer a personal apology to exophase.

The post of mine quoted above was in no way justified or warranted, nor were my comments in prior posts in which I stated or implied you did not read my posts to which you were quoting and commenting.

Sorry, exophase, you deserved better treatment than this and I do apologize for having treated you badly and leading you to have an otherwise unhappy experience here today

 

[Exophase]

Thank you.. In response: I feel like I've learned a lot about this stuff today, even at some resistance courtesy of my own stubbornness I think I have a knee-jerk reaction to statements that seem too absolute, but after talking to some others to help me explain some of the things you've described it looks like it really is pretty absolute. I'm just going to leave it at that and stop picking at what-ifs on a topic I don't know enough to really give relevant examples for

 

[MisterMac]

Just wanted to take a public moment here to reflect on this post of mine and offer a personal apology to exophase.

The post of mine quoted above was in no way justified or warranted, nor were my comments in prior posts in which I stated or implied you did not read my posts to which you were quoting and commenting.

Sorry, exophase, you deserved better treatment than this and I do apologize for having treated you badly and leading you to have an otherwise unhappy experience here today

I believe the prophecy once said the day IDC is fallible - the world will begin to end.

It's been a pleasure gents!

PS:

Loving this discussion exo & IDC and PM too!
Keep discussing!

 

[sequoia464]

However who wants a big ass cray with a working evaporation cooling waterfall like how they were made?

I would love having one of those in the den - two minor problems though.

1. Electric bill
2. The little woman would kill me.

 

[myocardia]

What matters, all that matters, regardless whether the node is labeled "32nm HKMG w/SOI" or "22nm 3D FinFet" or "Maple Node" or "Pineapple Node", are the electrical properties (the parametrics) of the various components (xtors, resistors, inductors, capacitors, etc) that have been implemented in the "node".

It is the node-on-node scaling of the electrical properties that matter most. If you can't or don't scale the electrical properties then the area scaling itself is nearly worthless (you do save on production cost). You can't shrink a chip and have it perform any better than its predecessor if the electrical parameters of the node involved in the shrink are not scaling.

So you think that being able to fit more transistors in the same area only benefits by decreasing costs? There are a lot of optimizations you can make to perf or perf/W that only involve using more transistors - GPUs and other very parallel devices are an excellent example of this. Since there are limits to die size that are both financial and physical smaller transistors means more transistors for all intents and purposes.

Where you have gone wrong here, Exophase, besides arguing with a CPU architect (who are all electrical engineers) over CPU architecture, is that Idontcare had already explained in the previous paragraph here what the definition of the words electrical properties means, when it comes to CPU architecture. If you don't change any of the properties of an xtor, that has to include speed, amperage, and voltage, making all of your arguments moot, since 50% more xtors at the same speed could not possibly use less power, unless you also change what he at first said wouldn't be changed, the electrical properties (this would primarily be amperage and voltage for any CPU). I know that you don't honestly think that 50% more xtors @ the identical amperage and voltage would use less power. I've seen some of your other posts around here, and you aren't dense.

edit: And don't feel bad, I've missed pertinent parts of Idontcare's posts before, and did the same thing myself.

 

[jpiniero]

That's rather pessimistic; the big boys (Intel, Samsung, and TSMC) have all talked about scaling to at least 5nm. Samsung talked about seeing scaling down to 1.2nm before they have to deal with the limits of physics.

There's a big difference between "possible" and "feasible for a sellable product". It does seem like the advantages of going to a smaller node are getting less, while the costs and the heat density are only going to get worse. I'm sure Intel will want to keep pushing, but the risk of getting overexposed is there.

 

[BTRY B 529th FA BN]

moore's law: Amd's end is near.

lol

 

[Hulk]

Physical scaling is very much alive, and will be for at least another 10yrs and maybe even longer still.

We can see our way down to 1.2nm with what we know of existing physics and chemistry.

Physical scaling is not about "can it be done?", that is the trivial solution because of course it can be done. But the challenge is "can it be done economically?"...and that is why it will take us 20yrs before we get to 1.2nm length-scales.

We will spend those 20yrs figuring out how to do what we can already do, but do it cheaply enough that profits can be made in doing it.

Below 1.2nm is the tough stuff, we require new physics to manipulate computing below that level if we intend to go there with the existing periodic table and chemistry know-how.

So, yeah, if I somehow convinced you (or anyone else) that I was trying to argue that scaling is dead then I miscommunicated somewhere along the way (my bad).

I find it amazing that we might be able to have a 1.2nm process. And don't get me wrong, I'm not doubting you one bit. I'm just amazed. If you consider that the Van Der Wals radii of a Si atom is 210pm, the diameter is 410pm. 1200pm=1.2nm This means that a part of the node that is this dimension would only be 3 atoms wide!

Even at 12nm, which we know is doable we're looking at a purpose built structure that is 30 atoms wide. It's simply amazing when you consider at this size scale absolute position and velocity become very fuzzy parameters.

But then again if you can actually get the atoms in the correct position (and this may be the best example of easier said than done in the world) then the things doing the work are the electrons and they are much, much smaller than the atoms.

 

[Keromyaou]

Since there are many knowledgeable forumers in this section, I would like to ask a question somewhat related to the subject in this thread. Since my field is not electrical engineering, this question might be irrelevant. Please forgive me in this case. I read somewhere in this forum that the quantum tunnel effect starts meaningful in the current 22nm node and that the lowering temperature of cpu has more significant impact on stability of performance in this generation than in previous ones (somebody recommended to reduce temperature significantly for overclocking 3770K). Then probably this applies to gpus as well. Current gpus (Kepler) are based on 28nm nodes. Before Kepler, there was Fermi gpus (45nm node) which were famous for high temperature (such as 90C or more). In fact many believed then that gpus were supposed to operate at such high temperature. However, in Kepler Nvidia seems to vigorously try to restrict power consumption and heat dissipation (such as temperature limit settings) unlike in Fermi. Is it because Nvidia wants to keep the temperature lower to stabilize gpus because of node size shrinkage? If this true, gpu of the next generation (Maxwell; 20nm node) will need more restrict temperature control?