Thanks for the detailed response as usual, IDC.
I'm confused, though. You seem to be saying that the node labels stopped reflecting reality, but because manufacturers were making features smaller than the nominal node size, not bigger. From a marketing perspective, if I were making a 0.30 μm chip I'd want to call it that, not 0.35.
And wouldn't the issue these days be more about cheating in the other direction, for that same reason? That is, doesn't Intel sound more "leading edge" if they talk about 14 nm for their next node even if, say, the smallest features are only 18 nm?
I think it is confusing because you (quite naturally) want the node label to mean something mathematical/numerical, and the reality of node labels doesn't fit neatly into that expectation. I was there too at one point, it really was jarring to have my expectations turned upside down.
But if you took away all the numbers and assigned the nodes streetnames or named them after fruit then you'd realize the label never mattered, ever, even in the pre-0.35um are when the physical dimensions meant something related to the node label.
What matters, all that matters, regardless whether the node is labeled "32nm HKMG w/SOI" or "22nm 3D FinFet" or "Maple Node" or "Pineapple Node", are the
electrical properties (the parametrics) of the various components (xtors, resistors, inductors, capacitors, etc) that have been implemented in the "node".
It is the node-on-node scaling of the electrical properties that matter most. If you can't or don't scale the electrical properties then the area scaling itself is
nearly worthless (you do save on production cost). You can't shrink a chip and have it perform any better than its predecessor if the electrical parameters of the node involved in the shrink are not scaling.
So at 0.35um the historic purpose of physical scaling, which was to improve the electrical properties, stop being a key enabler. You couldn't just shrink the xtor by 10% physically and get a 10% better transistor. You had to do other stuff, materials science engineering, to actually get the transistor to be 10% better electrically (including physically shrinking the gate length more than one would otherwise expect they needed to).
Physical scaling was, and is, still tied to metrics of cost control, production expenses. And physical dimensions still factor in the electrical properties of the devices (a 22nm 3D FinFet is its existing dimensions and not larger for electrical reasons).
This is why there can be so much variation between companies which claim to have the same process node. No two nodes are the same, even when they have the same node label. The difference is seen at every level, the physical dimensions are not the same, nor are electrical parametrics. But they will still use the same node label. (and that was true even before 0.35um)