AMD Magny-Cours...

[Idontcare]

Originally posted by: bfdd

Originally posted by: VirtualLarry

Originally posted by: RussianSensation
Very impressive that they got 12 cores onto 1 die considering AMD is always behind in manufacturing process compared to Intel.

You mean two dies. In an MCM package.

They're really going down that path after all the shit they talked on Intel for it?

Why yes. Yes they are.

Although in their (AMD's) defense I don't explicitly recall anyone with authority from AMD speaking ill of Intel's MCM approach...they just spoke candidly about how they felt their architecture was best-suited at the time to a monolithic integration approach.

I do distinctly recall the faithful brigades of non-AMD employee folks who repeatedly touted MCM being a fail approach, not a true quad core, blah blah blah.

It just goes to show that you should never-say-never and you really don't want to throw stones at other people's glass houses because the day may come when you find yourself in the position of having to justify why you are moving into a glass house too.

 

[Triskain]

AMD's MCM approach is certainly much more robust than Intel's. At least the dies are connected directly on the packaging with a high speed Hypertransport link. Not as good as having a monolithic processor but way better than using the FSB.

 

[exar333]

Originally posted by: Triskain
AMD's MCM approach is certainly much more robust than Intel's. At least the dies are connected directly on the packaging with a high speed Hypertransport link. Not as good as having a monolithic processor but way better than using the FSB.

So your saying C2Q was much slower than PhI because of this? Oh wait...

The HT link will make a difference as you scale with more cores, but again, the MCM approcah can work if you take the time to make it right.

 

[Idontcare]

Originally posted by: Triskain
AMD's MCM approach is certainly much more robust than Intel's. At least the dies are connected directly on the packaging with a high speed Hypertransport link. Not as good as having a monolithic processor but way better than using the FSB.

Originally posted by: ExarKun333

Originally posted by: Triskain
AMD's MCM approach is certainly much more robust than Intel's. At least the dies are connected directly on the packaging with a high speed Hypertransport link. Not as good as having a monolithic processor but way better than using the FSB.

So your saying C2Q was much slower than PhI because of this? Oh wait...

The HT link will make a difference as you scale with more cores, but again, the MCM approcah can work if you take the time to make it right.

Let me take a stab at explaining this.

Efficiency of processing parallelized applications are roughly characterized by two orthogonal aspects - coarse vs. fine grained code and inter-process communication (IPC) bound vs. unbound (i.e. contention).

In HPC applications, as well as server enterprise, a 2x2 matrix model suffices to communicate the high-level categorization of one's parallel application and choice of hardware.

Now as you can see in my hastily put together matrix there are two axis, one is determined by the application of interest (course vs. fine grained) and the other is determined by the communication topology of choice (as this determines latency and bandwidth).

Now we can see that for those applications which are not excessive in their demands on the IPC topology (FSB or HT) it really won't matter which architecture one chooses when it comes down to scaling efficiency, as such the architecture with the highest single-threaded performance will also end up being the processor with the highest multi-threaded performance (for the apps with low IPC demands, regardless whether they are course or fine grained applications).

Cinebench, povray, etc, a whole host of desktop applications tend to be IPC unbound, and hence the choice of going MCM and using the FSB for communication topology versus going monolithic and using internal data buses on the CPU for communication topology does little to change the performance of the cpu's in handling most multithreaded desktop applications.

Conversely we can have an application which is IPC sensitive, lots of information/data is transmitted and required by each thread in order for it to get on with the next iteration of computations. In this case single-threaded performance can end up being a poor indicator of multithreaded performance because the scaling efficiency ends up being IPC bound.

Here are some examples of the communication topology impacting the scaling efficiency depending on one's choice of architecture.

http://i272.photobucket.com/al...chBenchmarkScaling.gif

http://i272.photobucket.com/al...3DBenchmarkScaling.gif

Suffice to say if you happened to be running an IPC bound application (which are common in the enterprise server and HPC markets) then you would have found yourself wanting to buy K10-based opteron chips to enable extraction of a higher level performance from your multicore system.

If you happened to be running an IPC unbound application (which are common in the desktop consumer market) then you would have found yourself wanting to buy an MCM core2duo-based chip to enable extraction of a higher level of performance from your system regardless of the applications graininess.

 

[bfdd]

Originally posted by: Idontcare

Originally posted by: bfdd

Originally posted by: VirtualLarry

Originally posted by: RussianSensation
Very impressive that they got 12 cores onto 1 die considering AMD is always behind in manufacturing process compared to Intel.

You mean two dies. In an MCM package.

They're really going down that path after all the shit they talked on Intel for it?

Why yes. Yes they are.

Although in their (AMD's) defense I don't explicitly recall anyone with authority from AMD speaking ill of Intel's MCM approach...they just spoke candidly about how they felt their architecture was best-suited at the time to a monolithic integration approach.

I do distinctly recall the faithful brigades of non-AMD employee folks who repeatedly touted MCM being a fail approach, not a true quad core, blah blah blah.

It just goes to show that you should never-say-never and you really don't want to throw stones at other people's glass houses because the day may come when you find yourself in the position of having to justify why you are moving into a glass house too.

That's true it was mostly the AMD fanboys doing most the trash talking bout AMD has said they are the only ones with a "true quad core" CPU. I'm to lazy to dig up stuff, but I'm pretty sure they've said it before which is a nice way of saying "your method sucks".

 

[Idontcare]

Originally posted by: bfdd
That's true it was mostly the AMD fanboys doing most the trash talking bout AMD has said they are the only ones with a "true quad core" CPU. I'm to lazy to dig up stuff, but I'm pretty sure they've said it before which is a nice way of saying "your method sucks".

I'm not on a mission here to say AMD is comprised of saints or anything, but I will just say that when we look to the darker PR moments from AMD in the past few years they tended to be aggressive comments from just a few individuals who in turn rather quickly vacated their positions of employment in the capacity they had held when they took it upon themselves to make those comments publicly.

(I'm thinking specifically of Mr. 40% guy)

 

[Viditor]

Originally posted by: bfdd

That's true it was mostly the AMD fanboys doing most the trash talking bout AMD has said they are the only ones with a "true quad core" CPU. I'm to lazy to dig up stuff, but I'm pretty sure they've said it before which is a nice way of saying "your method sucks".

Not all MCMs are created equal...
The reason those "fanboys" talked trash about Intel's MCM on C2Q was because of the routing.
In Intel's C2Q MCM package, all cache traffic had to go back through the FSB between the 2 dual cores on board...in other words:

core1 - core2 = direct
core2 - core3 = through FSB
core1 - core3 = through FSB
core1 - core4 = through FSB
core2 - core4 = through FSB
core3 - core4 = direct

If you had a dual socket C2D system, it would be exactly the same speed as the cores on the single die. The big advantage then was that you would spend less for some of the software licenses (they are charged per socket, not per core).

That said, an MCM for Nehalem would be designed very different. In fact, it would be far more similar to Magny-Cours.

BTW...AMD actually said that they had wanted to design an MCM several years ago (instead of releasing the first iteration of Barcelona), but that the cost of the R&D was beyond them at the time. So no, AMD has never been dismissive of MCMs per se...

 

[bfdd]

IDC, I know I just find it funny they're going this path after the "true quad core" stuff. Viditor, It's still MCM all the same.

btw, I'd like to point out, I'm not hating on the actual CPU. It's quite impressive especially after over clocked. I could really careless if it is MCM or not, I just find it ridiculous all the hate Intel got for their MCM, yet this seems to be ok.

 

[Viditor]

Originally posted by: bfdd
IDC, I know I just find it funny they're going this path after the "true quad core" stuff. Viditor, It's still MCM all the same.

btw, I'd like to point out, I'm not hating on the actual CPU. It's quite impressive especially after over clocked. I could really careless if it is MCM or not, I just find it ridiculous all the hate Intel got for their MCM, yet this seems to be ok.

I didn't really see any hate, though I did read some ridicule...
But my point really was that not all MCMs are the same...just as all CPUs aren't the same.
I agree with you that using the term "true quad core" is a red herring and doesn't really work here.