Technically you will always have one core which is the slowest. Simple consequence of having >1 core. It is the slowest core which becomes the clock-limiting logic circuit for the overall monolithic IC. I know you know this
Technically you will always have one core which is the slowest. Simple consequence of having >1 core. It is the slowest core which becomes the clock-limiting logic circuit for the overall monolithic IC. I know you know this
'Disabled' was a poor choice of words. What he did was to use AMD Overdrive to independently overclock the other individual cores. I cannot recall what he did with that specific core, whether it remained at stock or was underclocked in some fashion.
Sorry I lost the link
because it would have been interesting for the early phenom adopters to play with. It's definitely a 'Brave New World' for the Phenom tweakers out there ...
IntelUser2000
Elite Member
- Oct 14, 2003
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Not true anymore. Barcelona's cache is now equal/smaller per MB compared to Merom's cache: http://www.chip-architect.com/...19_Various_Images.html
Things like the IMC and the HTT bus logic is taking up quite a lot of space too.
The core logic on the Barcelona is actually smaller in die size than the Conroe/Merom core.
If the Shanghai's 10-20% faster than Barcelona predictions are in SpecCPU, than it'll still be behind Conroe/Penryn per clock in integer for single thread.
- Sep 16, 2007
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Thanks for the link, seems you are correct about the IMC and HTT logic taking a sizable space on AMD CPUs, and about the cache density improvements on Barcelona.
About the SpecCPU performance predictions, I don't know really. What is important is how it will perform in everyday applications, games, encoding etc. So on those apps even a 10% increase will allow Shanghai to compete nicely with Penryn.
Originally posted by: Idontcare
Technically you will always have one core which is the slowest. Simple consequence of having >1 core. It is the slowest core which becomes the clock-limiting logic circuit for the overall monolithic IC. I know you know this
Sure. I meant a significant difference. If you had fine enough granularity in clock speed measurement and consistent tests, you'd find no two cores are ever the same. The intended audience of that post wasn't you or me.
The picture Tom's used for that article made me laugh.
Cool, I didn't know that
Originally posted by: heyheybooboo
'Disabled' was a poor choice of words. What he did was to use AMD Overdrive to independently overclock the other individual cores. I cannot recall what he did with that specific core, whether it remained at stock or was underclocked in some fashion.
Sorry I lost the link
These guys appear to be RMAing CPUs because they're not OCable enough. That's some nice ethics they've got.
- Sep 16, 2007
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I've found the thread on XS forums:
2400MHz, IMC@1980MHz, HT@1100MHz, RAM=440 4-4-4-4 2T:
2600MHz, IMC@3120MHz, HT@2160MHz, RAM=480 5-5-5-5 2T:
Notice how the L3 cache latency changed from 51ns when IMC was clocked at 1980Mhz to 33ns at 3120MHz IMC frequency.
The CPU frequency is 200Mhz higher, but that is not enough to cause the huge decrease in L3 latency (35%!).
Now I want to see a 3.2GHz Shanghai with 6MB L3 cache and IMC at 3.2GHz also
P.S The full and very long Phenom OC thread can be checked Here
Originally posted by: Kuzi
I've found the thread on XS forums:
2400MHz, IMC@1980MHz, HT@1100MHz, RAM=440 4-4-4-4 2T:
2600MHz, IMC@3120MHz, HT@2160MHz, RAM=480 5-5-5-5 2T:
Notice how the L3 cache latency changed from 51ns when IMC was clocked at 1980Mhz to 33ns at 3120MHz IMC frequency.
The CPU frequency is 200Mhz higher, but that is not enough to cause the huge decrease in L3 latency (35%!).
Now I want to see a 3.2GHz Shanghai with 6MB L3 cache and IMC at 3.2GHz also
P.S The full and very long Phenom OC thread can be checked Here
Kuzi, without diving into the links you provided (I will do that in time though) can you tell me why (official AMD party-line or enthusiast speculation) the IMC is so vastly underclocked on stock Phenom parts?
I was under the impression that this was intentional to manage the TDP budget. I.e. clock the IMC lower (less power consumption) so you can turn around and clock the cores higher (increasing power consumption) such that for the same total power consumption you balance IMC latency versus core performance and maximize the overall platform performance.
But I am beginning to wonder if I am just making this up and it never actually was part of the AMD strategy.
Hmm, the thread is 51 pages. Was he able to run a more meaningful benchmark on the machine while the IMC was overclocked? If the system is able to perform something complex at these settings, that would be juicy information indeed.
Also, given that AMD couldn't run the IMC and logic core synchronously, (for whatever reason,) why didn't they at least make them differ by some easily manageable multiplier like 1/2 rather than fixing the IMC at an arbitrary 1800mhz? I'm no expert, but round numbers have a special place in my heart.
I just realized why this all sounds so familiar. In the very first incarnation of the Athlons, when it was in a Slot form, (!) AMD couldn't produce L2 Cache at high frequencies. I'm talking about the Pentium-3 equivalent generation, 500-950 MHz range.
The top few speed grades had to run with a multiplier of 2X between the core+L1 and the L2 cache. Guess what? They scaled poorly, because the core was always starved for data. The next revision, with new and improved synchronous L2 cache, was a performance monster that propelled them straight through the P4/AthlonXP generation.
I'm greatly oversimplifying, but I hope we see a similar boost when they improve this generation's bottleneck.
The top few speed grades had to run with a multiplier of 2X between the core+L1 and the L2 cache. Guess what? They scaled poorly, because the core was always starved for data. The next revision, with new and improved synchronous L2 cache, was a performance monster that propelled them straight through the P4/AthlonXP generation.
I'm greatly oversimplifying, but I hope we see a similar boost when they improve this generation's bottleneck.
My FUD ...
'Synchronicity' and the AMD 200MHz reference clock, multipliers, memory divisors, etc., started out the window with DDR2/AM2.
AM2+ has thrown it out the window. The L3/IMC is contained on a 'variant' of the northbridge that now runs at its own frequency. AFAIK L1/2 cache still runs at cpu speed. I guess (!) a series of instructions (algorithms) handles the relationship between the 'triad' (cpu/cache - IMC/cache - memory)
When coupled with the split power planes it seems like this is AMD Bizzaro Land. But I think there is reason to their madness.
Since AM2 AMD is undergoing a series of platform transitions. With AM2+ we have the independence of the 'triad' and the split power planes.
I think this configuration (and transition) is a necessary step to ... Fusion.
I hope this made sense - I gotta run ...
'Synchronicity' and the AMD 200MHz reference clock, multipliers, memory divisors, etc., started out the window with DDR2/AM2.
AM2+ has thrown it out the window. The L3/IMC is contained on a 'variant' of the northbridge that now runs at its own frequency. AFAIK L1/2 cache still runs at cpu speed. I guess (!) a series of instructions (algorithms) handles the relationship between the 'triad' (cpu/cache - IMC/cache - memory)
When coupled with the split power planes it seems like this is AMD Bizzaro Land. But I think there is reason to their madness.
Since AM2 AMD is undergoing a series of platform transitions. With AM2+ we have the independence of the 'triad' and the split power planes.
I think this configuration (and transition) is a necessary step to ... Fusion.
I hope this made sense - I gotta run ...
exar333
Diamond Member
- Feb 7, 2004
- 8,518
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Originally posted by: heyheybooboo
I stumbled across a forum post (which I can't locate now) whereby someone disabled 'core2' of the Phenom in AMD Overdrive and succeeded in a generous overclock and control of the IMC/northbridge. It was difficult to determine if this was 'factual or FUD' because of the tone of the post.
And I was of the general impression that errata 298 was partially based on the 'flush' (or lack thereof) of the L2 in one core that effectively created a memory addressing conflict within the cache structure of the cpu.
Someone above my paygrade will have to determine the connection (if there is one) with the nb/imc speed limitation of 1.8GHz(?)
AMD could gain some traction with an upfront explanation of the problem and their success in addressing it with B3 ... but I guess I'm asking for too much
90nm - X2 6400+ @ 3.2GHz ""Windsor""
65nm - X2 5400+ @ 2.8GHz ""Brisbane""
I don't know how to characterize the clockspeed issues with the Phenom but have always assumed it related to the 1.8GHz limitation of the imc/nb
Doesnt anyone else here find it interesting that as the process gets smaller, the top clock-speed is reducing? That is exactly the opposite of Intel. The other poster may be right that AMD milked so much out of 90nm that they didnt prep well enough for 65nm and smaller. This is a disturbing tend, to be sure. Hopefully they can buck this trend and get back on track with 45nm. What worries me is that we have seen zero test demoes of 45nm. Intel was demoing these 45nm over a year before they became retail to show it was maturing well. AMD seems pretty close-mouthed, that is usually not for the best.
Originally posted by: Kuzi
I've found the thread on XS forums:
2400MHz, IMC@1980MHz, HT@1100MHz, RAM=440 4-4-4-4 2T:
2600MHz, IMC@3120MHz, HT@2160MHz, RAM=480 5-5-5-5 2T:
Notice how the L3 cache latency changed from 51ns when IMC was clocked at 1980Mhz to 33ns at 3120MHz IMC frequency.
The CPU frequency is 200Mhz higher, but that is not enough to cause the huge decrease in L3 latency (35%!).
Now I want to see a 3.2GHz Shanghai with 6MB L3 cache and IMC at 3.2GHz also
P.S The full and very long Phenom OC thread can be checked Here
That xtremesystems forum link is by far the best information on Phenom overclocking I have seen, thanks! It is interesting to see that Toms Hardware didn't properly disable the TLB fix in their benchmarks after reading that. It seems like a very complicated process to change anything on those MSI boards.
- Sep 16, 2007
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You are correct in your assumption. From the excellent OC tests that KTE posted at XS forums, power consumption does go way up with increased IMC and HT speeds. So that is one reason why AMD would clock Phenom IMC so low at 1.8GHz.
Originally posted by: Foxery
Hmm, the thread is 51 pages. Was he able to run a more meaningful benchmark on the machine while the IMC was overclocked? If the system is able to perform something complex at these settings, that would be juicy information indeed.
Yes check the 71st post on this Page
He ran many many benches with Phenom at 2.6Ghz, IMC at 3120Mhz, and HT at 2160Mhz. Remember these tests were done about 3 months ago, so the BIOS probably was not 100% optimized yet.
And I think his RAM was running only in single channel mode at the time he tested, could have been a mobo or Bios problem not sure. So can't compare these results with anything else really
I thought they purchased the SRAM chips from other suppliers. Didn't the Pentiums of the time do similar things? Also, IIRC the top speed grades were actually at 1/3 clock for the L2; the slowest CPU speeds had 1/2 clock.
Correct. The Argon and Pluto cores had MCM with L2 cache. 700MHz and below and the L2 ran at 1/2 multiplier. 850MHz and below had L2 cache that ran at 2/5 (not quite 1/2) multiplier. Above 850MHz the L2 ran at 1/3 multiplier.
Apologies for the Wiki link, but having owned 26 Athlons at the time I was merely looking for a link which I can vouch for based on my experience. The wiki link here is correct insofar as the cache discussion.
http://en.wikipedia.org/wiki/Athlon
Who here remembers the "goldfinger"?
Would that be possible, LV3 cache is obviously easier to yeild as it is considerably slower, maybe it's cost trade off? Though even with double the total cache I expect the Shanghai derivatives to be smaller then the current Bareclona.
No, your forgeting to incorporate the fact that alot of the Bareclona die is core logic, doubling the cache on Bareclona would not make it 570mm2, 1MB of cache at the 65nm node shouldn't be much more then 25mm2 each so your looking at close to 400mm2, still way too costly for anything besides the MP environment though.
At 45nm 8MB of total cache with the Bareclona core as it is now would probably come in at the 210-270mm2 range quite doable.
On the topic of cache sizes, I was always surprised that AMD didn't spin a teh uber cache size Opteron targeted at that 8xxx server market. Sure the diesize would be intentionally large, sub-600mm^2, but it would mostly be large regions of cache arrays that could be fused off to maintain yields as well as down-binning to desktop SKU's to ensure the whole mix was saleable material.
I never quite settled on a rationale for why AMD only differentiated their Sempron chips by cache size for the lower end but not for their upper end Opterons (and now Barcelona's).
- Sep 16, 2007
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It is my understanding that as the processor gets more cores, a large shared cache pool becomes more important. I believe even Intel will start producing desktop processors with large L3 caches in the future.
As many people mentioned before, the L2 cache size in AMD CPUs is less important because of the integrated memory controller. It's just that at the current Barcelona/Phenom state, the IMC is running too slow at 1.8GHz, which increases L3 cache latency and lowers overall performance. Hopefully this problem will be rectified when Shanghai is released. And who knows there could other variables slowing Phenom right now.
In Intel's case it's more cores and more threads per core (Nehalem = 2 threads/core via SMT).
Speaking of hyperthreading, does AMD have any plans to boost the threads/core > 1? They need something like this on their roadmap for 2H/09, don't they?
- Sep 16, 2007
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Notice how most desktop applications (not synthetic) today don?t use more than two cores, and even the ones that do make use of +2 cores, only get a minor boost in performance (going from 2 to 4 cores), this is generally speaking of course. So the more cores you have it becomes harder and harder to make use of the extra cores, how many programs are out right now that give 4x performance from 4 cores vs a single core.
As to Hyperthreading in Nehalem (8x threads), my guess is that the increase in performance will be minimal for two reasons. First it will never be as effective as having 8 real cores, and second is what I mentioned above, that in general most applications today don?t get much benefit even from 4 cores. On the server side it might be very different and my guess Nehalem with Hyperthreading will show it?s true strength there.
As to AMD my guess is that they plan to have two quad-core processors on the same die (non-native) what Intel has been doing with their CPUs for a while. You know it?s cheaper and easier to do, but even at 45nm the die size would be too big, so maybe they need to wait till 32nm to do that. Good luck AMD.
I agree completely about hyperthreading...in fact, I don't know of a good reason for Intel to be bringing it back (unless it helps with the CSI interface in some way).
As to AMD's upcoming 8 and 16 cores CPUs, I don't know...
What we know so far is:
1. They are part of the fusion project in that they will be designed for modularity. This lends credence to your predicition of an MCM in that with all of the different variables (xCPU + xGPU = 8 cores), it would be VERY expensive to design and produce all of them...
2. On the other hand, we also know that they will utilize DC architecture and have a crossbar switch. This has always been a feature of monolithic design only (in fact I don't know how you could do it with an MCM). There's also the problem of how you deal with the on-die memory controller in an MCM...
BTW, while an MCM is cheaper from a yield standpoint, it's not necessarily cheaper overall (they are very expensive to design, which is why AMD doesn't have one).
Phynaz
Lifer
- Mar 13, 2006
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Because Nehalem is very wide and SMT will show some nice performance gains.
I'd be very interested in what makes you think an MCM is any more expensive to design that any other cpu architechture. Especially since the "expense" would be man-hours, and Intel did it in nine months. There's also the "expense" of of AMD not being in the quad core market for a year.
AMD doesn't have an MCM becuase they picked the wrong strategy. Need I post the link to the Hector Ruiz quote that he wished he had gone MCM instead of native?
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