Mate, you absolutely picked the wrong Forum...
1. The majority of people in this Forum overclock...there's nothing "whacko" about them.
2. Motherboards are in the Motherboard Forum!
Nemesis 1
Lifer
- Dec 30, 2006
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Viditor - You may find this interesting.
http://www.channelregister.co.uk/
The thing I found interesting was the 45nm metal gates bit for AMD /IBM only.
Well spotted...
The co-development began in Dec 2002 for a 65nm process. They both brought engineers, IBM donated part of their East Fishkill Fab, and AMD paid for their half of that equipment (~$250 Million, which was a large portion of their credit line back then).
It was extended in 2004 for 45nm, and extended again in 2005 for 32nm and 22nm. Currently it's extended through 2011...
I would bet that the reason they've opened it up to Memory Makers is that AMD has just sold off almost all of their Spansion ownership, so they are no longer competitors.
Wait, I thought only Intel had this High-K metal gate technology on their 45nm shrink and AMD wasn't going to have High-k until their 32nm shrink. According to this article AMD will infact have it on 45nm. Did they just manage to speed up adoption of the technology faster than people thought?
If this is true this is good news for Shanghai and Bulldozer!! :thumbsup:
It would probably be better for AMD to take the hit and wait just a little longer, then jump straight to this 32nm tech. For the first time, they'd be ahead of Intel in process tech.
Nemesis 1
Lifer
- Dec 30, 2006
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Well befor ya get to excited about AMD being ahead of intel at 32nm . Best check some statements by IBM . Intel showed a a 32nm waffer already done . Weres IBMs pics.
When intel announced they were doing High K and metal gates . IBM jumped in and said ya we have that to. The differance is Intel showed a product. IBM just talked.
Metal gates on AMD 45nm . isn't anywere near ready .
Also IBM is saying their High K metak gates chip is better. If they use fin fet I agree IBMS 45nm well be better.
BUT! Intels 32nm is going to be 3d gates I am sure IBM will be also. Its whos first.
I am most interested in If IBM goes gate first or last. Be interesting if they solved the melting metal of the gates with their process.
Nemesis 1
Lifer
- Dec 30, 2006
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NO intel has said all along that 3D gates would appear @ 32nm. Intel also said Metal gates @ 45nm . I will get a link and post it.
1) http://hardware.slashdot.org/a.../06/12/224207&from=rss
Date 2009 thats 32nm.
2) http://developer.intel.com/tec...-gate-demonstrated.htm
This one says after 45nm process
3) http://www.nano.org.uk/forum/v...f10153d92a8db837b#2695
This one says 32nm. 09.
4) http://www.technewsworld.com/story/51049.html
This is ware people got 3D gates @ 22nm. But it really doesn't say that. It says 32nm maybe 22nm .
1) http://hardware.slashdot.org/a.../06/12/224207&from=rss
Date 2009 thats 32nm.
2) http://developer.intel.com/tec...-gate-demonstrated.htm
This one says after 45nm process
3) http://www.nano.org.uk/forum/v...f10153d92a8db837b#2695
This one says 32nm. 09.
4) http://www.technewsworld.com/story/51049.html
This is ware people got 3D gates @ 22nm. But it really doesn't say that. It says 32nm maybe 22nm .
I'm not sure what you mean by a 32nm wafer, but I don't think Intel has even made it to a 32nm SRAM yet (at least they haven't announced it).
A 32nm wafer of what? I'm unclear what they had that was 32nm...
Was it mearly a testing of being able to create a 32nm anything, or was it of actual SRAM test modules?
ZOXXO
Golden Member
- Feb 1, 2003
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Phynaz
Lifer
- Mar 13, 2006
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You know what, now that I think about it, you're right.
I was thinking that Intel has one major changeover for the next two process nodes, immersion and 3d gates both at 32nm, then they get to coast to 22nm.
AMD on the other hand, must undergo the change to immersion at 45nm, maybe coast to 32nm, and then need another major change at 22nm.
Nemesis 1
Lifer
- Dec 30, 2006
- 11,366
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Ya. I believe thats correct as far as Intels planning goes . IF all goes well. Intel had it easy from 65nm to 45nm . The next change will be immersion @ 32 and 22.
So intel will beable to Actually have the equipment to produce a quality 3-D metal gate on
S silly using a high K sudstrate.
The HighK and Metal gates @ 45 was a hugh break for Intel. Being Able to go 1 extra generation befor immersion . It gives the Intel braintrust time to really fine tune the immersion process for 32nm and latter 22nm .
Since we already know Intel has working 32nm wafers I think Nehalem C is going to kick ass. Not in performance so much other than the fact clocks are going to go threw the roof. Many factors for this improvement . If you read the provided materials I find the switching on the 3dgates themselves most interesting. Switching speed is greatly inhanced and Electromechanical Forces.Are greatly enhanced because of the three gates. The other factor for 32nm to scale higher is if you paid attention to the supplied links . Is the Channel length can be shortened considerably. This will all aid in 32nm scaling higher. The other factor In having the abilities for shorter channels . Is intel can tune the channels for differant processor usage. They been able to do this befor but not to this degree .
The really big deal about this 32nm. For me isn't going to be the performance which is going to be great . Its going to be the hugh gain in power efficiency were going to see. I believe it well be the biggest leep ever and it dam well better be or intel can forget about Nehalem C 16 core 32 thread @ 32nm. Than Geshner 16 core up to 32cores 64 threads @ 22nm. Intels 32nm has to work or Nehelem C and Geshner are in trouble.
So intel will beable to Actually have the equipment to produce a quality 3-D metal gate on
S silly using a high K sudstrate.
The HighK and Metal gates @ 45 was a hugh break for Intel. Being Able to go 1 extra generation befor immersion . It gives the Intel braintrust time to really fine tune the immersion process for 32nm and latter 22nm .
Since we already know Intel has working 32nm wafers I think Nehalem C is going to kick ass. Not in performance so much other than the fact clocks are going to go threw the roof. Many factors for this improvement . If you read the provided materials I find the switching on the 3dgates themselves most interesting. Switching speed is greatly inhanced and Electromechanical Forces.Are greatly enhanced because of the three gates. The other factor for 32nm to scale higher is if you paid attention to the supplied links . Is the Channel length can be shortened considerably. This will all aid in 32nm scaling higher. The other factor In having the abilities for shorter channels . Is intel can tune the channels for differant processor usage. They been able to do this befor but not to this degree .
The really big deal about this 32nm. For me isn't going to be the performance which is going to be great . Its going to be the hugh gain in power efficiency were going to see. I believe it well be the biggest leep ever and it dam well better be or intel can forget about Nehalem C 16 core 32 thread @ 32nm. Than Geshner 16 core up to 32cores 64 threads @ 22nm. Intels 32nm has to work or Nehelem C and Geshner are in trouble.
Phynaz
Lifer
- Mar 13, 2006
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I was mistaken.
After reading further, I discovered that nobody gets to coast to 22nm.
At 22nm the polysilicon channels are too narrow to deposit current metal gate materials. Something new will be needed.
It looks like Intel can use a process that is significantly the same at 32nm as their 45nm process.
Now I just need to figure out why I thought AMD needs a new process at 32nm.
After reading further, I discovered that nobody gets to coast to 22nm.
At 22nm the polysilicon channels are too narrow to deposit current metal gate materials. Something new will be needed.
It looks like Intel can use a process that is significantly the same at 32nm as their 45nm process.
Now I just need to figure out why I thought AMD needs a new process at 32nm.
How thin can they make them? at 22nm isn't that like 10 silicon atoms wide?
Edit: I was wrong. Given 2 angstroms or so for a si-si bond, it's like 100 atoms wide.
Edit: I was wrong. Given 2 angstroms or so for a si-si bond, it's like 100 atoms wide.
Guys we are getting very very close to some very very exciting times.
I'm talking about hitting a wall at 5nm; possibly getting to 4nm; then they're toast. After that the electrons can simply tunnel through the insulator like in a zenor diode.
What will they do?
Next 10 years will be very, very exciting.
I'm talking about hitting a wall at 5nm; possibly getting to 4nm; then they're toast. After that the electrons can simply tunnel through the insulator like in a zenor diode.
What will they do?
Next 10 years will be very, very exciting.
They will probably start adding more layers instead. First 2, then 4, then 8. If no one else has patented it I'll call it Jones' Law
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