AMD ingnots, sliced ´TBread´ with the crusts cut off

[Liquid3D]

This response speaks to most of the replies above. First, I just want to clearify one misconception, I don't think I mentioned any "conspiracy", nor do I beleive there is some organized "plot" to withhold manufacture techniques from the public. I realize there has to be confidentiality, to protect the integrity of processses unique to AMD and Intel. And in my defensiveness, having been harshly attacked (not particularly in this forum, but another).

Second, I do appreciate constructive critiism. I'm struggling to perfect my writing style, and as I enjoy writing technical articles above all, there's certainly room for improvement. Upon rereading the article, I've found it's wrought with inaccuracies, and semantic ambiguities.
I do not feel attacked, and am grateful for those qualifying their criticims so I do not respond defensively. I don't just have a mild interest in the subject, I want to delve into it fully. I have subscribed to EETimes, BYTE, Semiconductor International, kuro5hin.org, Semiconductor Online, IEEE Computer Society, Silicon Strategies, MDRonline, Supercomputing Online, etc. These trade journals, although difficult to interpret at times, do seem to contain more of the type of information I seek.

The Editor at Madsrimps asked how I wanted to "edit" the article, and as Shalmanese mentioned, I did not touch the original, as I wanted to preserve the integrity of the original, mistakes and all. What I've done is ad an amedment qualifying some errors, and clarifying amgiguities. I've corrected one or two sentences, and expalined my inspration.
Unfortunately this was not my best work. In fact wasn't even mediocre. Recently I have been been diagnosed with blood sucrose levels above 175. I'm not making excuses, but I had kept feeling tired, loosing my train of thiought. As I say, this is not an excuse it's simply the truth. Since breaking my back in a NORBA downhill event, my health has deteriorated in many ways. I'd never expected to have high blood sugar. I'm sure my addiction to a daily pint of Ben & Jerrys contributed to this.
I'd rushed this into publication, and did not "fine tune" it. I worked hard, editing, rephrasing sentences, and prargraphs, however; I missed many structural errors. To Patrick (PM) and Wingznut I would be honored, and most appreciative if you were to email me at; keith.suppe@verizon.net providing as much information in reference to the article, or in microprocessor fabrication in general, and perhaps allowing me to ask a few questions as to source material. The last thing I intended to do was pertetuate any false information. My commitment to scientific theory, is critical to my chosen feild, Neurophilosophy (Neuroscience). One reason I've such an interest in Computer Science (including it's manufacture) is due to the role of AI in Neuroscience. There's currently no better analogical model for cognitive processes then software such as PDP (Parallel Distrubutive Pocessing) or ISP (Intelligent Signal Processing). These softwares actively emulate synaptic activity (firing frequency/strength ratios) recreating cognitive prcessesses such a Learning, Memory, and Bahvior. Computational Science not only utilzes software, but many explores the physical simliarities betwen the physicalities of microporcessors, and the brain.

And in so far as my subscribing the center wafer producing higher quality cores, there still seems to be some disgreement. Lynx516 wrote; The whole wafter is used but due to the probablility of errors in the waffer increases the further out you go you are more likely toget dead chips not ones which work but dont OC so far.
This in fact promulgates thatn theory, which was so strongly criticized. And this was one reason I beleived Austins Guide to be accurate. And it was from similiar descriptions I extrapolated perhaps the "reason" the outer wafer yeilded slightly "less overclockable" Cores, this was perhaps how different speed processors were chosen. And it seems that theory is sound in it's premesis, ergo it's conclusion.

Finally I have two question for anyone whom feels qualified to answer;
1.) in my describing the origin of .13 micron measurement, I defined this as the gate "WIDTH" across those "lines" along which voltage (binary information) travels along the core's microcircuitry. I've read twice in the last few days this measuremant actually describes "gate LENGTH". If the latter is in fact true, then could this be explained to me, using a visual analogy?

2.) In my description of the 157nm (acutally it's 248nm for .13 micron) process. Is this the ultraviolet light wave-LENGTH? Hence, the shorter the wavelength, the smaller the gate "WIDTH /LENGTH"? AND the smaller these lines imaged, then etched into the wafer surface as the resist is washed away, the less voltage required, and the faster these (binary pulses?) voltage travel. So that the smaller the die shrink, less voltage is required, and faster the processor becomes?
Thank you, all for your comments and criticisms, especially your etiquette whilst challanging, clarfying, and/or correcting aspects of my article! 🙂

 

[sgtroyer]

I'll take a whack.

First, a little basic information. Any integrated circuit consists of transistors and wires to hook them up. For a given process, there are rules describing the minimum size of a transistor, the minimum width of wires, the minimum spacing, etc. Moore's Law has been enabled by the exponential decrease of all of those dimensions. So why is smaller faster? Intuition tells us that a signal travelling a shorter distance takes less time, but this isn't actually the dominant factor. Larger wires present a larger capacitive load, which means they take longer to transistion from a zero to one, or one to zero. Smaller wires = less capacitance = faster chip. There's a second reason why smaller processes are faster, but first we'll have to talk about the transistor.

The transistor is what drives signals to zero and one, it does the actual work of a processor. A faster transistor can produce more current, discharging the capacitace more quickly. The speed of a transistor is proportional to the Width divided by the Length. A wider transistor provides a wider path for the electrons, so more electrons flow. A shorter transistor sort of produces a shorter path for the electrons, so more electrons flow. (It's actually a little more complicated than that, but we'll brush over the details). So the fastest transistor is very wide and has a very short length. We can make both the width and length as large as we want, but the minimum is determined by the design rules I talked about above. So for fast circuits, you almost always use the minimum length, to produce the fastest circuit. Since the minimum channel length, as it's called, is the dominant factor in circuit speed, that's the rule we use to refer to a fabrication process. The .13um process has a minimum channel length of .13um.

So how does this relate to 157nm or 248nm, or whatever? .13u, or 130nm, refers to the dimensions of a physical part of the circuit, the channel length. 157nm refers to the wavelength of light used to produce the image to fabricate the part. 157nm light can create a picture of a .13um gate, or a .18um gate, or a 5um gate, if you so desire. If you try to go much lower, however, it gets really tricky, because light doesn't image well at all below its own wavelength. This is one of the challenge to going to smaller processes, although not the only challenge, by far. By using light with a smaller wavelength, smaller features can be resolved. Smaller features enable faster circuits.

Is that clear? It's complicated stuff. I'll try and find a link that goes into more detail on device physics, for those who are interested.

On a side note, I want to say that I'm very suspicious of the theory that chips from the center of the wafer are much faster than the outer chips. I won't say it's not possible, but I've never heard such a thing. In general, there is a small variation between circuits on the same chip, a somewhat larger variation between chips on the same wafer, a much larger variation between wafers in the same lot, and a very large variation between wafers from different lots. In other words, I would expect a much larger variation between a chip produced on Wednesday and one produced the next Friday than between a chip at the center of the wafer and one at the edge of the same wafer.

It seems there are a lot of theories floating around that are based on intuition or guesswork, but with no physics to back them up. This is complicated stuff, and you can't just reason based on what seems right.

Magazines like EE Times are great. I read it too. But EE Times mostly talks about the business of electrical engineering, not the technology. EE Times doesn't really teach you anything, it's only useful if you already understand the technology. I'd recommend looking at some textbooks to learn about device physics and fabrication. That will give you the theoretical background to understand what you read in the journals. If you live near a university and have access to their library, that would be the easiest route. The other great source is online course materials from some universities, such as Stanford, MIT, and Berkeley. They have notes and often even videos of the lectures online. It's great what you can come up with for free.

Again I prattle on...

 

[Wingznut]

I had this thread open from much earlier today. I just sat down, ready to write out a lengthy reply. Good thing that I checked to see if anyone had replied in the meantime. 😉

Very nice post, sgtroyer. 🙂

 

[pm]

I agree with everything Steve wrote above me. I'll try to add additional comments around what he wrote so eloquently.

And in so far as my subscribing the center wafer producing higher quality cores, there still seems to be some disgreement. Lynx516 wrote; The whole wafter is used but due to the probablility of errors in the waffer increases the further out you go you are more likely toget dead chips not ones which work but dont OC so far. This in fact promulgates thatn theory, which was so strongly criticized. And this was one reason I beleived Austins Guide to be accurate. And it was from similiar descriptions I extrapolated perhaps the "reason" the outer wafer yeilded slightly "less overclockable" Cores, this was perhaps how different speed processors were chosen. And it seems that theory is sound in it's premesis, ergo it's conclusion.

A long time ago, in an industry very young, the idea that the fastest chips came from the center of the wafer was correct. Now, it's not. On an 8" or 12" wafer, there is a small, but somewhat higher probability of a failed chip on the periphery of the wafer due, typically, to dislocations/defects in the silicon cystalline matrix caused by stress/strain, but once you get in from the immediate edge, there is no less of a statistical likelihood of failure (or a slower than typical part) than in any one part of the wafer. Generally what determines a chip's speed on the same wafer more than anything else is which part of the stepped image it is in. The stepper works by "stepping" a lithographic image of usually multiple chips (depends on the size of the chip) like a stamp. Using the case of having four chips in a stepped image, usually each one will consistently be faster or slower than the others depending on where it is in the image. For example, the upper left one may consistently be the fastest. This has to do with transistor orientation on the critical paths, and the incidence of light into the mask that creates the transistors for that path.

Still, Steve's right. Variation is smallest between parts on the same wafer, no matter where they are on the stepped image. Then there is a larger statistical variation between wafers in the same lot. And the largest between different lots.

1.) in my describing the origin of .13 micron measurement, I defined this as the gate "WIDTH" across those "lines" along which voltage (binary information) travels along the core's microcircuitry. I've read twice in the last few days this measuremant actually describes "gate LENGTH". If the latter is in fact true, then could this be explained to me, using a visual analogy?

Width and length on a transistor are, in my opinion, backwards from how a normal person would probably term them. The "length" of a gate is the distance between the source and the drain and is the small resolvable feature on a given process. When people talk about what process generation something is, they are referring to the transistor length. The width of the transistor is the distance that the gate travels across the transistor in between the source and the drain. I have hunted for a diagram, but I can't seem to find one.
So I hand-drew one and put it on my website. It's extremely rudimentary, but it will work for purposes of illustration. It's here

I've always thought this length/width thing is backwards... but not as backwards as the whole "source/drain" "current direction" thing.

2.) In my description of the 157nm (acutally it's 248nm for .13 micron) process. Is this the ultraviolet light wave-LENGTH? Hence, the shorter the wavelength, the smaller the gate "WIDTH /LENGTH"? AND the smaller these lines imaged, then etched into the wafer surface as the resist is washed away, the less voltage required, and the faster these (binary pulses?) voltage travel. So that the smaller the die shrink, less voltage is required, and faster the processor becomes?

Steve answered this very well, but I'll add my comments.

157nm is the wavelength of the light that comes out of the laser. The shorter the wavelength, the smaller things that you can lithography draw with the light. If you try to draw a transistor that is smaller than the wavelength of the light used to draw it through the mask, the image of the transistor will be blurry. So if you are drawing a 0.13um square using a 193nm laser, it will end up looking like a circle. Through the use of various tricks such as OPC, and to a lesser extent phase shifting, you can still get the shape that you want without upgrading the laser to a smaller (and more expensive) wavelength... up to a point anyway. Link to OPC company webpage and to another one on Synopsys's page with a more graphic example.

As far as voltage, signalling and die shrinks, I wouldn't have termed it the way that you did, but what you said is fundamentally correct. It's worth noting that reducing voltage is something is forced on the industry due to reliability concerns. The circuitry doesn't "require" less voltage. It's more like if you give the circuit a higher voltage, it will break either immediately, or in time. Voltage reductions reduce the operating power of the part, and improve the reliability. But it is much harder to design robust circuitry for lower voltages even with the improvements in process technology.

 

[PrinceXizor]

All I've got to say is...this is the most informative forum thread I've read so far. An excellent thread....I hope it continues for a long while.

P-X

 

[Wingznut]

I'm not sure what more I can add... So, I'll add a pic. 🙂

I don't think this will top pm's picture, but here is an actual pic of a transistor. Where the oval is (where Anand is pointing out the electron flow) would be the gate length. And yes, it is backwards than one would naturally think.

Now, when we are talking gate length on the .13µ process, the smallest gates have lengths that are actually much smaller than 130nm.

Originally posted by: PrinceXizor
All I've got to say is...this is the most informative forum thread I've read so far. An excellent thread....I hope it continues for a long while.

Just keep asking questions. 🙂

 

[Harabecw]

This is not exactly related to all of this but...
Is quantum computing getting advanced enough to get the attention of Intel and the like?

 

[sgtroyer]

I'm out of my depth here, but my impression is no. Quantum computing looks really attractive on paper, especially for certain types of problems (like cracking cryptopgraphy), but it's fiendishly difficult to actually implement. I would guess it will be confined to the research laboratory, if not just physicists imaginations, for quite some time yet.

 

[Harabecw]

quite some time, yes, but does it have the potential?
PC's took ~50+ years to get where we are, but the major advance was in the last 20 or so years. why is that?

 

[PrinceXizor]

Quantum Computing is in its extreme infancy, we're still talking about the "basics" Think of the creation of a single transistor to change one bit from1 to 0. That is where we are in the quantum arena, a bit far away from the likes of microprocessors.

P-X

 

[Sahakiel]

Originally posted by: Harabecw
PC's took ~50+ years to get where we are, but the major advance was in the last 20 or so years. why is that?

private industry.

 

[PrinceXizor]

Originally posted by: PrinceXizor
Quantum Computing is in its extreme infancy, we're still talking about the "basics" Think of the creation of a single transistor to change one bit from1 to 0. That is where we are in the quantum arena, a bit far away from the likes of microprocessors.

P-X

Actually, I'm going to revise my statement.

Its more like we are at the experimental design stage of the very first vacuum tube. This is the first iteration of a quantum component that will function in the way we hope. The transistor was really a breakthrough in the huge shrinking and economizing of this first iteration. Quantum computing hasn't even gotten to a first iteration yet...to my knowledge anyway.

P-X

 

[pm]

Once I have permission from the author, I will respost any email correspondence that I think might be interesting on here.

 

[Eskimo]

Lots of stuff to reply to, not a lot of time. Bear with me if I'm repetitive. In no particular order:

Gate width vs. length when we are talking about critical dimensions. I'm guilty of switching these two terms around, you asked for a simple graphical explanation. I have no graphics but here's the lowdown. The correct term is length, it's called length because it's describing the length carriers have to travel between source and drain. Someone earlier was explaining how integrated circuits are formed/designed I believe. I might say width because to define that length a geometrical line is drawn on a mask. If i'm a metrology engineer for a mask shop I would measure the width of that line. If i was looking at a cross sectional SEM picture of the transistor I could also call the gate dimension a width even though electrically it is a length.

Die marking ballyhoo. Blown way out of proportion, there is information on the die, not a whole lot it will tell an enthusiast about the specifica performance of their chip. A lot of those numbers and letters are simply a way to track specific chips from wafer fabrication and through assembly and test. The actual information you want is associated by those ID numbers in databases within AMD or whoever's chip you are talking about. Not every AMD engineer could tell you what every last letter and number stands for, even if my NDA didn't prevent divulging such information I probably couldn't either.

Center vs. edge die. There is a mixture of truth/fiction here. First it is true that in the manufacturing process it is usually true that die yield at the edge of the wafers is lower than that at the center. This is not speed yield we are talking about but rather functional yield. As in the chip doesn't work at all. These are usually defect related caused by the need for mechanical handling at the edge. Someone correctly told you about the small statistical difference in within wafer variation. Even this very small difference can have some effect but it is not always radial, there are a variety of patterns. Process control and reduction of variability in the processes is the goal of every fab engineer. There are several radially dependent processes inside the fab that could possibly effect yield. Some film deposition tools show center to edge variations as do CMP, dry etch and any spin on process (resist, ARC, low k). These variations are very small in modern systems.

Wish I could go into more detail but supper calls 😉

 

[DAPUNISHER]

I and I believe many others would love to read the e-mails that were exchanged or have someone continue to elaborate upon this topic so bump!

 

[jmke]

please read his new editorial Here
answers alot of the questions asked & points raised!